Verilog programming specification-reset

Verilog programming specification-reset

There is a way to learn, the content of this article from Verilogthe reset signal in the programming specification to the reset FPGAscene in the middle.

The essence of the content comes from the book "Communication IC Design", only for integration for learning.

Reset in Verilog Programming Specification

Rule 1: It is forbidden to use the following codes to realize synchronous reset.

Under normal circumstances, any module can reset synchronously and asynchronously. But in general, a single global synchronous reset circuit or a single global asynchronous reset circuit must be used in the same clock domain.

And most ASICdesigns usually need FPGAto be verified on the above, and FPGAthe handling of synchronous and asynchronous reset is inconsistent.

In order to ensure the universality of the code, the asynchronous reset method is mandatory for ASIC projects , so the following synchronous reset methods are prohibited;

always @ ( posedge clk ) begin
    if (syn_rst) begin
        ;
    end else begin
        ;
    end
end

Rule 2: It is recommended to use a synchronous asynchronous reset signal , and the realization circuit is as shown in the figure below:

In the above figure, it ext_asy_rstis an external reset signal. Although asy_rst_12p88the falling edge is synchronized with the clock, it is still used as an asynchronous reset.

In principle, every clock source outputs an asynchronous reset signal.

The standard Verilogprocedure for the above circuit is as follows:

always @ ( posedge clk_122p88 or posedge ext_asy_rst ) begin
    if ( ext_asy_rst ) begin
        rst_shft[1:0] <= 2'b11; 
    end else begin
        rst_shft[1:0] <= {rst_shft[0], 1'b0};
    end
end

assign asy_rst_122p88 = rst_shft[1];

The standard asynchronous reset statement rules are as follows:

always @ ( posedge clk_122p88 or posedge asy_rst_122p88 ) begin
    if ( asy_rst_122p88 ) begin
        ;
    end else begin
        ;
    end
end

Rule 3: Unless a third-party IP is formulated, all asynchronous resets must use a uniform effective level;

Application scenarios of reset in FPGA

For the ASICcase, any synchronization register unit needs to be reset; for the FPGAcase, there is no exact rule.

In fact, many FPGAunits do not need to be reset, because the reset signal usually needs to occupy FPGAinternal channel resources, and the load of the reset signal is usually a lot, which is likely to cause difficulties in the reset signal wiring, overall performance degradation, and increase in compilation time.

Therefore FPGA, the reset that can be omitted in the design is omitted as much as possible .

In addition FPGA, the reset signal levels of the registers are usually set uniformly in the advanced options, which can further save the reset resource overhead.

Here are a few reset examples that can be omitted, but they are not absolutely applicable.

Shift Register

Under normal circumstances, only need to reset the first stage of shift register, and then hold for several cycles, the shift register is completely reset, without adding a reset to each shift unit.

If every unit needs to be reset, it will inevitably lead to a pure Dflip-flop implementation, and the FPGAmanufacturer provides IP mapping.

Counter for frequency division

The frequency divider circuit is a multi-bit counter. If the initial phase does not need to be controlled, there is no need to initially reset the counter, just add each clock 1. For example, the following is a 2**Ncounter divider.

reg [N-1:0] cnt;
always @ ( posedge clk ) begin
   cnt <= cnt + 1'b1; 
end

Moore type state machine output

For Moorethe output of the type state machine, as long as the state machine is reset, the next cycle will be reset. Failure to reset the storage state may cause （X）the problem of instability in the back shock . This problem can be solved by assigning initial values ​​to registers, for example:

reg[N-1:0] current_state = 0;

Synchronous reset and asynchronous reset

In reset design, a common question is whether the circuit adopts synchronous reset or asynchronous reset.

XilinxThe recommended circuit adopts synchronous reset, but the author adopts synchronous asynchronous reset. The following table explains the advantages and disadvantages:

The following is the asynchronous reset synchronization method recommended by the author, as shown in the figure:

The implementation code is as follows:

module reset_sync(
	input clk,
 	input  rst_x_in, //
 	output reg rst_x_out //
 	);
reg rst_x1,rst_x2,rst_x3;
wire rst_x_pulse;
 
always @(posedge clk)begin
	rst_x1<=rst_x_in;
	rst_x2<=rst_x1;
	rst_x3<=rst_x2;
end
 
assign rst_x_pulse=rst_x2|rst_x3;
always @(posedge clk)
	rst_x_out<=rst_x_pulse;
endmodule

After

Some of the above designs have been encountered before, whether it is synchronous reset, asynchronous reset, or asynchronous reset synchronization; but there has been no rule, and it is not clear what type of reset should be used when.

When designing in the past, I followed my own ideas, how I wanted to do it, and how I did it;

There is an urgent need for a set of practical ones Design rules, not only to save time and avoid duplication of design, but also to follow the industry standards; a unified standard will greatly improve efficiency.

In short, the reset design:

According to my understanding, all synchronization with the asynchronous clock recommended at the end is the most suitable solution.

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