1. Verilog code specification
1. Assign initial value
Do not assign initial values to variables when declaring them. The initial value assignment operation should be completed in the reset state. It is also recommended that the register variables use the reset terminal to ensure that when the system is powered on or in disorder, the system can be restored to the initial state through the reset operation. It is recommended to use positive edge logic for the clock and negative edge logic for reset. When resetting, all signals in the statement block should be given initial values, and relevant signals should not be missed.
2. About the always statement
(1) Do not use the rising edge and falling edge logic of the same clock in the two always blocks unless it is absolutely necessary, otherwise it will introduce relatively complicated problems of clock quality and timing constraints
(2) It is forbidden to use both edges of the clock as the trigger condition at the same time in an always block. Compilation and simulation may be carried out according to the designer's idea, but such circuits are often not synthesizable, or the circuit function after synthesis will not meet expectations
(3) Do not have multiple parallel or irrelevant conditional statements in an always block, use multiple always to describe them separately
3. About clock and asynchrony
Synchronous design should be used as much as possible in the design. When it is necessary to use asynchronous logic, the signals between different clock domains must be processed synchronously, and related signals cannot be used directly, otherwise a metastable circuit will be generated.
4. About synthesis
In general, signal variables should not be directly used for operations such as multiplication *, division /, and remainder %. After these operators are synthesized, the structure and timing are often not easy to control. The relevant optimized ip module or the integrated module in the process library should be used. But constants of parameter type can use this kind of operator, because the compiler will calculate the result of constant operation at the beginning of compilation, and will not consume redundant hardware resources.
5. About instantiation
During instantiation, the signal connected to the input end can be a reg or wire type variable, and the signal connected to the output end must be a wire type variable. But when the port signal is declared, the input signal must be a wire type variable, and the output signal can be a reg type or wire type variable. When multiple modules are instantiated, the module name comes first, and the instantiated name follows, and the instantiated names cannot be the same.
2. Some important principles
1. When modeling sequential circuits, use non-blocking assignment
2. When modeling the latch circuit, use non-blocking assignment
3. When writing combinatorial logic with always block, use blocking assignment
4. When establishing sequential and combinational logic circuits in the same always block at the same time, use non-blocking assignment
5. Do not use non-blocking assignment and blocking assignment at the same time in the same always block
6. Do not assign values to the same variable in multiple always blocks
#Following the above principles will help to write synthesizable hardware correctly, and can eliminate 90%~100% of the competition risk phenomenon that may occur during simulation.
3. Timing error
Continuous use of combinatorial logic may cause timing errors due to long data paths,
Workaround: Add registers on long paths for data buffering.
1. Combination logic is rarely used for high-speed data processing, because the data rate is too fast, which is prone to competition risks.
2. For high-speed data stream processing, perform a cache first,
3. For high-speed data processing, try to use non-blocking statements, because the use of continuous blocking statements will cause timing errors when the data flow is too fast. Originally, the result of blocking statements is the same as that of non-blocking statements.
4. Complicated calculations cannot be performed in one step.
Personal summary, there may be mistakes.