caveat:
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Resolution process:
Seeing this warning, I couldn't locate where the problem occurred. I found it on the Internet and located it as follows:
On the compilation report, select the location as shown in the figure below to know where it appears.
The appearance of the word "hierarchies" is basically a problem of module instantiation. During general instantiation, this warning will be issued if any connection is not drawn , not connected , or the bit width does not match . You can find it by locating to the instantiation file or observing the RTL view, but it is not so easy to find for a large project!
As you can see from the figure, my problem is that the usedw signal has a total of 6 bits, of which usedw[5:1] does not fan out, that is, there is no lead wire. Look at the code, because the usedw bit width is 6bit, and the bit width is defined as 1bit when it is defined.