触发器：
(1)D锁存器
library ieee;
use ieee.std_logic_1164.all;
entity dff1 is
port(clk:in std_logic;
d:in std_logic;
q:out std_logic
);
end;
architecture bhv of dff1 is
signal q1:std_logic;
process(clk)
begin
if clk'event and clk='1'
then q1<=d;
end if;
q<=q1;
end process;
end bhv;
法2：
library ieee;
use ieee.std_logic_1164.all;
entity test1 is
port(
clk,d:in bit;
q:out bit
);
end;
architecture bhv of test1 is
begin
process(clk,d)
begin
if rising_edge(clk) then q<=d;
end if;
end process;
end bhv;