用VHDL编写数码显示

数码显示器

 数码管显示原理:

 程序:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity smg is

port(

a:in std_logic_vector(3 downto 0)

y:out std_logic_vector(6 downto 0)

);

end;

architecture bhv of smg is

begin

process(a)

begin 

case a is

when "0000"=> y<="0111111";--0

when "0001"=> y<="0000110";--1

when "0010"=> y<="1011011";--2

when "0011"=> y<="1001111";--3

when "0100"=> y<="1100110";--4

when "0101"=> y<="1101101";--5

when "0110'=> y<="1111101";--6

when "0111"=> y<="0000111";--7

when "1000"=> y<="1111111";--8

when "1001"=> y<="1101111"--9

when others=> y<="0000000"--灭

end case;

end process;

end bhv;

原理图:

 数码管仿真图:

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转载自www.cnblogs.com/lhkhhk/p/11828928.html
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