Chip clock system

Recorded at the clock-related study notes (S3C2440 ARM-CHIP-32bit for example)


Problems introduced:

Q: CPU running fast, but the peripherals running more slowly, how to match their clock source it?  

A: They have different clock sources.




Heart of a computer chip to the motherboard provides a clock signal, the oscillator is connected to the other components of the clock signal.


S3C2440 has three clock sources:

  • FCLK: a CPU core.
  • HCLK: apparatus for the AHB bus, a memory controller such as a CPU core, high-performance device interrupt controller, LCD controller, DMA, and the USB host module.
  • PCLK: apparatus for the APB bus, such WATCHDOG, IIS, I2C, PWM timer, MMC interfaces, ADC, UART, GPIO, RTC and SPI low-speed devices.



These sources generating process can be described briefly:

  1. When just powered system, FCLK is equal to the external clock input. 12M or 24M is usually crystal of. Wait stable oscillator output (in this case FCLK = Fin), reset signal returns high, CPU starts executing instructions.
  2. Then open the MPLL software manner (phase locked loop circuit for increasing the system clock frequency), to raise the clock frequency 12M or 24M to 100 to 400 (directed to S3C2440).
  3. And then, by setting the number of registers (set divider) can be changed FCLK, HCLK, the clock frequency of PCLk ratio (for example 1: 2: 2)

In this way, the other two clock sources also increased. It is appreciated that, when the system is running, is working together three clock sources, each providing different clock frequencies for different devices.

Of course, some equipment is not very "satisfied" with these frequencies, it will be set or some frequency asynchronous mode, or divide the work themselves.




The system clock given (typically PCLK) is counted, when the count is full, it will generate an interrupt.

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