2440 clock system

Selected input clock
S3C2410 / S3C2440 clock control logic external oscillator which can then generate an internal clock source circuit, may be used directly to provide an external clock source, which is selected by setting pin can be seen that the clock source 2440 two, a crystal oscillator is the OSC (upper left corner), can be input via the clock pin EXTCLK, then OM [3: 2] selectors,

see diagram below, we can see that when the crystal source JZ2440 12Mhz, see on FIG crystal 12MHz enter through the OM to the MPLL, using the P [5: 0], M [7: 0], S [1: 0] frequency to control the output of the crystal 12MHz into UPLL by OM, using the P [5: 0], M [7: 0 ], S [1: 0] to control the output frequency,

according to the principles graph that OM2, OM3 00, 00 according to the chip that when using an external crystal oscillator as the clock input source is 12Mhz

different application of different clock source
clock control logic for the whole chip are three clock: of FCLK (for cpu core), HCLK (AHB devices on the bus), PCLK (a device on the bus APB)
AHB bus: main module for high-performance

APB bus: mainly used for low-bandwidth peripherals connected to the peripheral

improved The method of the system clock of
CPU core S3c2440 operating voltage is 1.2, the frequency can reach 300Mhz, an operating voltage of 1.3V, frequency can reach 400Mhz, in order to reduce electromagnetic interference in general, lower frequencies can be connected to an external crystal, then through the PLL system clock is increased, S3C2440 has two PLL: MPLL and UPLL, MPLL for generating FCLK, HCLK, PCLK clock high frequency operation, UPLL operating frequency for providing USB, PLL works as follows

1. power few after milliseconds, the crystal oscillator figure (or OSEs) output stability, is equal to the oscillator frequency of FCLK this time, the reset signal becomes high level
2. Read MPLL provided, this time FLCK to stop, lock time length determined by the register LOCKTIME
after 3.LOCKTIME, MPLL normal output, the CPU in the new work FCLK

Programming registers:
lock time LOCKTIME generally take the default value

input is used to set the ratio of the external crystal and FCLK relationship of the column, as shown in the formula


for setting the clock ratio between

the default reference value

if HDIVN is not equal to 0, CPU asynchronous mode must be set , CPU execution work in the HCLK, below

Code:
Start.S

.text
.global  _start
_start:
      /*关闭看门狗*/
      ldr r0,=0x53000000
      ldr r1,=0
      str r1,[r0]
      /*初始化时钟*/
      /*设置locktime*/
      ldr r0,=0x4C000000
      ldr r1,=0xFFFFFFFF
      str r1,[r0]
      /*设置工作于异步模式下*/
      mrc p15,0,r0,c1,c0,0
      orr r0,r0,#0xc0000000
      mcr p15,0,r0,c1,c0,0
      /*设置时钟比例*/
      ldr r0,=0x4C000014
      ldr r1,=0x5
      str r1,[r0]
      /*设置提高时钟倍数*/
      ldr r0,=0x4C000004   
      ldr r1,=(92<<12)|(1<<4)|(1<<0)
      str r1,[r0]
      /*判断是nand启动还是nor启动*/
      mov r1,#0
      ldr r0,[r1]
      str r1,[r1]
      ldr r2,[r1]
      cmp r1,r2
      ldr sp,=0x40000000+4096
      moveq sp,#4096
      streq r0,[r1]
      bl main
halt:
    b halt

led.c

#include "s3c2440_soc.h"
void delay(volatile int d)
{
   while(d--);
}
int main(int argc, char * * argv)
{ 
  int val = 0;
  int tmp;
  GPFCON&=~((3<<8)|(3<<10)|(3<<12));
  GPFCON|=((1<<8)|(1<<10)|(1<<12));
  while (1)
 {
		tmp = ~val;
		tmp &= 7;
		GPFDAT &= ~(7<<4);
		GPFDAT |= (tmp<<4);
		delay(100000);
		val++;
		if (val == 8)
			val =0;
		
 }
  return 0;
}