After the read and write us achieve DDR3 controllers IP core we find, read and write commands are shared with some lines, so that the read / write required time-use IP cores command bus, a specific method of FIG. Fig.
As shown above, we can time-division signal transmission will app_cmd A7_wr_ctrl A7_rd_ctrl modules and the IP core app_cmd signal. For app_addr signal A7_wr_ctrl and A7_rd_ctrl module, we can when not in use it is set to 0 , and we will app_addr signal A7_wr_ctrl A7_rd_ctrl module and perform bitwise or result is the IP core app_addr. Similarly, IP cores can also A7_wr_ctrl app_en A7_rd_ctrl modules and bitwise OR app_en obtained.
code show as below:
1 assign app_en = app_rd_en | app_wr_en ; 2 assign app_addr = app_rd_addr | app_wr_addr ; 3 assign app_cmd = (app_wr_en == 1'b1) ? app_wr_cmd : app_rd_cmd ;
In summary,
As indicated above, we have completed the interaction with the read and write module IP core, but with the addition read, write enable signal is generated at the same time, will result in app_addr app_en while effectively and, bitwise or above will fail, we can not allow read / write start signal is generated simultaneously, in order to solve this problem, we can add an arbiter to control the production of read, write enable signal, block diagram below.
To complete the arbiter shown above, we can set a state machine, after the reset, can go directly to the arbitration state, waiting to be read in the arbitration state, a write request, when a request arrives, that is, into the corresponding state the appropriate action, and only read in the arbitration state, the conflict will not write.
code show as below:
1 // *********************************************** *************************** 2 // *** name: arbit.v 3 // *** do Xun: tedyma 4 / / *** blog: https://www.cnblogs.com/tedymafpga/ 5 // *** date: 2019-08-10 6 // *** description: DDR3 arbitration module 7 // ***** ************************************************** ******************* . 8 Module1 Arbit . 9 // ======================== < port> ========================================== 10 ( 11 //---------------------------------------- System 12 is INPUT Wire SCLK, // clock _50Mhz 13 is INPUT Wire RST, // reset, active low 14 // INPUT --------------------------------- -------- 15 iNPUT Wire wr_req, // input in 16 iNPUT Wire rd_req, . 17 iNPUT Wire wr_end, 18 is iNPUT Wire rd_end , 19 //output ---------------------------------------- 20 output wire wr_cmd_start , //输出out 21 output wire rd_cmd_start 22 ); 23 //========================< 信号 >========================================== 24 reg [3:0] state ; 25 reg wr_flag ; 26 reg rd_flag ; 27 reg wr_cmd_start_r ; 28 reg rd_cmd_start_r ; 29 //========================================================================== 30 //==宏定乿 31 //========================================================================== 32 parameter IDLE = 4'b0001 ; 33 parameter ARBIT = 4'b0010 ; 34 parameter WR = 4'b0100 ; 35 parameter RD = 4'b1000 ; 36 //========================================================================== 37 //== 输出 38 //========================================================================== 39 assign wr_cmd_start = wr_cmd_start_r ; 40 assign rd_cmd_start = rd_cmd_start_r ; 41 42 43 //========================================================================== 44 //== 状濁机 45 //========================================================================== 46 always @(posedge sclk) begin 47 if(rst) begin 48 state <= IDLE; 49 end 50 else begin 51 case(state) 52 IDLE: state <= ARBIT; 53 ARBIT:if(wr_req == 1'b1 )begin 54 state <= WR; 55 end 56 else if(rd_req == 1'b1)begin 57 state <= RD; 58 end 59 WR: if(state == WR && wr_end == 1'b1)begin 60 state <= ARBIT; 61 end 62 RD:if(state == RD && rd_end == 1'b1)begin 63 state <= ARBIT; 64 end 65 default:state <= IDLE; 66 endcase 67 end 68 end 69 //----------------------------------------------- 70 always @(posedge sclk) begin 71 if(rst) begin 72 wr_flag <= 1'b0; 73 end 74 else if(state == WR && wr_flag == 1'b1)begin 75 wr_flag <= 1'b0; 76 end 77 else if(wr_req == 1'b1)begin 78 wr_flag <= 1'b1; 79 end 80 end 81 //----------------------------------------------- 82 always @(posedge sclk) begin 83 if(rst) begin 84 rd_flag <= 1'b0; 85 end 86 else if(state == RD && rd_flag == 1'b1)begin 87 rd_flag <= 1'b0; 88 end 89 else if(rd_req == 1'b1)begin 90 rd_flag <= 1'b1; 91 end 92 end 93 //========================================================================== 94 //== wr_cmd_start_r 95 //========================================================================== 96 always @(posedge sclk)begin 97 if(rst) begin 98 wr_cmd_start_r <= 1'b0; 99 end 100 else if(wr_flag == 1'b1 && state == WR)begin 101 wr_cmd_start_r <= 1'b1; 102 end 103 else begin 104 wr_cmd_start_r <= 1'b0; 105 end 106 end 107 //========================================================================== 108 //== rd_cmd_start_r 109 //========================================================================== 110 always @(posedge sclk) begin 111 if(rst) begin 112 rd_cmd_start_r <= 1'b0; 113 end 114 else if(rd_flag == 1'b1 && state == RD)begin 115 rd_cmd_start_r <= 1'b1; 116 end 117 else begin 118 rd_cmd_start_r <= 1'b0; 119 end 120 end 121 122 endmodule
simulation
The rd_req wr_req and top module as input signals. As shown in the simulation works as follows fanatics.
Waveform: