FPGA studio will be open to you on xilinx FPGA using a mig IP read and write control of DDR3 through five articles designed to make everyone learn faster and use DDR3.
Based on this experiment and completion Arty Artix-35T FPGA development board of Digilent.
Software Vivado 2018.1.
First: introduction of DDR3 and mig
1 DDR3 Introduction
With Micron MT41K128M16 example to introduce DDR3.
Through the above information we can know the address bit wide DDR3 memory capacity, Row, Column and Bank of. Development Board selected MT41K128M16 DDR3 capacity of 16Megx16x8banks = 2048Mb = 2Gb.
1.1 DDR3 named
We know DDR3 capacity, package, speed rating and other information through the Configuration, Package, Speed ... and so named for DDR3.
1.2 DDR3 internal structure
1.3 Interface
Use xilinx mig IP to control data read and write DDR3 DDR3 above information we can understand.
2 mig Introduction
As shown above, mig (Memory Interface Solution) IP consists of three parts User Interface Block, Memory Controller and Physical Layer. IP side of the interface (Physical Interface) connector DDR3, the other side is the user logic control interface (User FPGA Logic). DDR3 want proper control read and write, we need the correct settings mig IP and correct logic control user interface logic.
2.1 mig user interface
For the meaning of the customer interface of mig we describe in "Part III --mig IP Interface Timing Analysis user logic to read and write" in detail.
3 DDR3 schematic and FPGA schematics
By schematics DDR3 we can know DDR3 supply voltage is 1.35V. DDR3 hung on the 34 bank FPGA.
FPGA studio will be open to you on xilinx FPGA using a mig IP read and write control of DDR3 through five articles designed to make everyone learn faster and use DDR3.