First, the purpose of the project
Writing the client, in accordance with the read control the main functions need to accept FIFO IP core logic, write the corresponding logic functions, the output of the controller should be in accordance with the timing FIFO IP core.
1, the user writes controllers
The following first to write controller for analysis. FIFO IP core reserved for write port includes two FIFO interface, which can be a cached data, another command can be cached. To ensure data is written in DDR3 SDRAM, no line where the amount of data and inconsistent burst length, we can save the data to be written into the first data in the FIFO, the FIFO command information related to a write command transmitted, so FIFO IP core can be ensured with the command after receiving, the data can be correctly transmitted burst length.
2, users write controller framework
You can see from the chart, the data to be written by the wr_en wr_data effective sign, we need to implement to generate the information needed by the write port FIFO IP core wr_data and wr_en enter in this module, and ultimately FIFO IP core write data port the FIFO flag to generate client write completion signal.
3, each variable description of the module
4, a timing diagram of the write control UE
Can be seen from the figure, we can determine the number of input burst length in accordance with the incoming data, when the end of input data, to generate the write enable command FIFO port information and the like. When the FIFO IP core after receiving the command FIFO command, data is written to the FIFO out DDR3 SDRAM, we can determine whether or not to complete the process according to the FIFO empty flag, when the rising edge of the data FIFO is empty logo appears, is considered All the sudden empty flag can be written to a DDR3 SDRAM, in which case we can generate a signal that the external module user_wr_end this burst write ends.
Calculated address: DDR3 is a 16-bit data address, the address is incremented by one each representing the 16-bit data is written, when it does 128-bit data eight 16-bit DDR memory.
Code:
timescale 1ns `/ 1ps // ******************************************* ******************************* // *** name: user_wr_ctrl.v // *** author: tedyma / / *** blog: https://www.cnblogs.com/tedymafpga/ // *** date: 2019-08-10 // *** description: You write logic, it requires only a small amount of control interface to control more many commands // **************************** ***************************** Module user_wr_ctrl // ================= ======= <port> ======================================== == ( the INPUT Wire SCLK, the INPUT Wire rst , input wire wr_en , input wire [127:0] wr_data , output wire p2_wr_en , output wire [127:0] p2_wr_data , output wire [15:0] p2_wr_mask , output wire p2_cmd_en , output wire [6:0] p2_cmd_bl , output wire [2:0] p2_cmd_instr , output wire [27:0] p2_cmd_addr , output wire user_wr_end , input wire p2_wr_empty ); // ------------------------------------------------ -------------------------- // - parametric // ---------------- -------------------------------------------------- -------- Parameter BURST_LEN = 64 ; // burst length Parameter start_addr = 0 ; // start address Parameter STOP_ADDR = 785.92 thousand ; // 1024 768-512 * (here set to 1024 * 768 resolution) 128 = 64 * 512/16 Parameter ADDR_ADD = 64 * 128 / 16 ; //Every time address the need to increase // ------------------------------------------ -------------------------------- // - signal definition // ---------- -------------------------------------------------- -------------- REG wr_en_r; REG [ 127 : 0 ] wr_data_r; REG p2_cmd_en_r; REG [ 27 : 0 ] p2_cmd_addr_r; REG [ . 6 : 0 ] data_cnt; REG p2_wr_empty_r0,p2_wr_empty_r1,p2_wr_empty_r2; reg user_wr_end_r ; //-------------------------------------------------------------------------- //-- 输出的接口信号 //-------------------------------------------------------------------------- assign p2_wr_data = wr_data_r ; assign p2_wr_en = wr_en_r ; assign p2_cmd_en = p2_cmd_en_r ; assign p2_wr_mask = 0 ; assign p2_cmd_bl = BURST_LEN ; assign p2_cmd_instr = 3'd0 ; assign p2_cmd_addr = p2_cmd_addr_r ; assign user_wr_end = user_wr_end_r ; //-------------------------------------------------------------------------- //-- 数据和写命令 //-------------------------------------------------------------------------- always @(posedge sclk) begin if(rst) begin wr_en_r <= 1'b0; wr_data_r <= 'd0; end else begin wr_en_r <= wr_en; wr_data_r <= wr_data; end end // ---------------------------------------------- ---------------------------- // - wr_cmd_en命令 // -------------- -------------------------------------------------- ---------- always @ ( posedge SCLK) begin if (rST) beginning p2_cmd_en_r <= 1 ' b0; end else if (wr_en == 1 ' b 0 == 1 && wr_en_r ' b1) beginning p2_cmd_en_r <= 1 'b1; end else begin p2_cmd_en_r <= 1'b0; end end //-------------------------------------------------------------------------- //-- 地址 //-------------------------------------------------------------------------- always @(posedge sclk) begin if(rst) begin p2_cmd_addr_r <= START_ADDR; end else if(p2_cmd_addr_r == STOP_ADDR && p2_cmd_en_r == 1'b1)begin p2_cmd_addr_r <=Start_addr; End the else IF (p2_cmd_en_r == . 1 ' B1) the begin p2_cmd_addr_r <+ = p2_cmd_addr_r ADDR_ADD; End End // ------------------------- ------------------------------------------------- / / - playing on the FIFO empty signal input of two shot (at top top module, also need two beats, the role is not the same) // -------------------- -------------------------------------------------- ---- Always @ ( posedge SCLK) the begin p2_wr_empty_r0 <= p2_wr_empty; p2_wr_empty_r1 <= p2_wr_empty_r0; p2_wr_empty_r2 <= p2_wr_empty_r1; end //-------------------------------------------------------------------------- //-- 用户结束信号 //-------------------------------------------------------------------------- always @(posedge sclk) begin if(rst) begin user_wr_end_r <= 1'b0; end else if(p2_wr_empty_r1 == 1'b1 && p2_wr_empty_r2 == 1'b0)begin user_wr_end_r <= 1'b1; Over presence begin user_wr_end_r <= 1 ' b0; than than endmodule
Second, the implementation of the UE reading
1, the client's read controller Introduction
After the FIFO controller reads the IP port reserved for the core two FIFO interface, which is a command FIFO, FIFO other data, we need to send corresponding information to the command FIFO, the IP core is detected command FIFO in the FIFO order , based on the command information corresponding to the transmission data to the data FIFO burst length, we detect enough data in the FIFO memory required amount of data, can be read out to the corresponding data.
2, the controller reads the user side frame
Client module requires a rd_start read as an input, after rd_start signal is valid, the command FIFO output module required p1_cmd_en, p1_cmd_bl, p1_cmd_instr p1_cmd_addr signal and, after the FIFO controller corresponding to the IP core based on the burst length information transmitted data to the data FIFO, we can according to the amount value determination data in the FIFO data p1_rd_count when the amount of data in the data FIFO is consistent with the amount of data required, we can produce p1_rd_en signal to the data FIFO, the data read in the data FIFO out.
3, port variables explained
4, the UE timing diagram of read control
As can be seen from Figure 4, when rd_start valid, generates a signal read port command FIFO needed, these signals are written into the FIFO read command at the end p1_cmd_en valid, then the controller sends a DDR3 IP core required data into the data FIFO read terminal, we can determine the amount of data in the FIFO data burst according to whether this value satisfies p1_rd_count, and then generate a final read-out has been met p1_rd_en this data burst, when read after the data signal may be generated user_rd_end.