SDRAM Controller (9) - Final Module

 Top-level modules of ADRAM:

 1. FIFO_read module:

Module block diagram:

 Waveform diagram:

 Use UART serial port to send

Reference: Communication protocol (1) - UART protocol

Need to rebuild a synchronous FIFO core

 code:

module FIFO_Read
(
	input 				sys_clk				,
	input				sys_rst_n				,
	input	[9:0]		rd_fifo_num			,
	input	[7:0]		rd_fifo_rd_data		,
	input	[9: