First of all
Then populated write their own code
After the save as to save their own folders
It will automatically pop up
Configuration
Assignments settings
After the first compilation
成功后processing start start testbench template writer
After going under the saved file, here is a simulation folder, find XXX.vt file, open, save as XX_test_tb.v. (Note saveas to the top-level folder) modify the contents of design documents for their own good test
After compiling again qutartus
After successful tools netlist viewer rtlviewer can see rtl netlist map.
After the tools runsimulationtools rtl level simulation
pop up
Tools options general edatooloptions
Add modelsim altera path
Here is the general quartus and bound together, found himself a bit, better looking.
After the tools runsimulationtools rtl level simulation
Then there is a problem, can not find test_tb
Back to qutartus.
Assignments settings
Test benches new
File name just add top-level file test_tb
Note Do not forget to fill in testbenchname
After recompiling
After the tools runsimulationtools rtl level simulation
Simulate start simulation work选择test_tb
Add wave, see (Note that this unit is ps, so you may want to run a long time to change, to be flexible and use the magnifying glass)
