Verilog basics: the use of task and function (2)

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Table of contents

4. Function declaration and call

4.1 Declaration of function

4.2 return value of function

4.3 function call

4.4 Rules for functions

4.5 Constant functions


4. Function declaration and call

        The purpose of function is to return a value, and then use it in an expression (that is, as an operand).

4.1 Declaration of function

        The syntax of a function declaration is as follows:

        Explanation of the function declaration:

        1. The first one is the grammar of Verilog-1995, and the input parameters and items in the function are declared after function_identifier;.

        2. The second is the grammar of Verilog-2001. The input parameters are declared inside function_identifier(); brackets, and the items in the function are declared after function_identifier(); which is an ANSI-C style statement.

        3. The items in the function include various types of variables (reg[signed], integer, time, real, realtime), event declaration, local parameter declaration and parameter declaration.

        4. A function that does not use automatic is static (Static). All input parameters and items in the function declared in the function are statically allocated memory, and they are shared for all concurrent executions of the same function.

        5. The function using automatic is dynamic and reentrant, and the emulator dynamically allocates memory for each concurrently executed function.

        6. function_range_or_type is used to declare the type of return value, which is optional. If not specified, it returns a 1-bit scalar by default; if specified, the type of the return value can be: [range][signed], integer, time, realtime, real.

        7. The function should have at least one input parameter.

4.2 return value of function

        When defining a function, a variable with the same name as the function is implicitly declared inside the function. It is a 1-bit reg by default, or specified with function_range_or_type. When the function returns, return this variable.

4.3 function call

        Function calls are used as operands in expressions. When a function is called, the order in which the input parameters are evaluated is indeterminate.

4.4 Rules for functions

        Compared with task, function has many restrictions. The following are the usage rules of function.

        1. The definition of function cannot contain any timing control statements, that is, #, @ and wait cannot be included. Because the function parameter input, calculation, and return are all completed in one time-step.

        2. The function cannot enable the task, because the task may contain timing control.

        3. The function contains at least one input parameter.

        4. function cannot contain any output and inout parameters.

        5. Non-blocking assignment (<=) cannot be used in function, and process continuous assignment cannot be used.

        6. Named events cannot be triggered within a function.

4.5 Constant functions

        The constant function is newly added to the Verilog-2001 standard and is used to calculate complex values ​​during elaboration. Constant functions require synthesis and simulation tools to compute the function's return value at compile time.

        Constant functions are very important to IP development. The purpose is to allow designers to add local parameters to a module. These local parameters are derived from the parameters passed when the module is instantiated.

        Let's consider a simple RAM model, in order to parameterize this model we need width of address, depth of storage and width of data. The width of the data must be passed to the model, but for the width of the address and the depth of storage, only one needs to be passed. If the width of the address is passed, the storage depth can be calculated by a constant function; if the storage depth is passed, the width of the address can be calculated by a constant function.

        In order to make tool vendors more accept constant functions, the Verilog Standardization Group (Verilog Standard Group, VSG) has added obvious constraints on constant functions, but there are no such constraints on regular functions. Constant functions are a subset of regular functions with the following requirements.

        1. Constant functions cannot contain hierarchical references.

        2. The constant function is defined in the calling module, and the parameter is a constant.

        3. A constant function can call a system function whose parameter is a constant expression, but cannot call other system functions.

        4. Constant functions will ignore system tasks.

        5. The parameters used by any constant function must be defined in advance.

        6. The parameters used by the constant function cannot be directly or indirectly affected by defparam.        

        7. Constant functions cannot be declared in the generate block.

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