The source file of the simulation task in Verilog and the corresponding simulation file of modelsim

Below is a simple Verilog code example that defines a task called addition_task that adds two input values ​​and stores the result in a register called sum. At the same time, a testbench file is used to instantiate the addition_task and simulate it.

// Example Verilog code with task simulation

module adder(
  input logic [7:0] a,
  input logic [7:0] b,
  output logic [8:0] sum
);

  // Task to perform addition of two inputs
  task addition_task(
    input logic [7:0] a,
    input logic [7:0] b,
    output logic [8:0] sum
  );
    begin
      sum = a + b;
    end
  endtask

  // Main logic
  always @* begin
    addition_task(a, b, sum);
  end

endmodule

simulation file

// Testbench to simulate the adder module
module adder_tb;

  // Instantiate the adder module
  adder dut(
    .a(a),
    .b(b),
    .sum(sum)
  );

  // Define inputs
  logic [7:0] a = 8'b00000001;
  logic [7:0] b = 8'b00000010;

  // Define outputs
  logic [8:0] sum;

  // Simulate for 10 clock cycles
  initial begin
    // Reset the module
    dut.rst_n = 0;
    #50;
    dut.rst_n = 1;

    // Wait for 1 clock cycle
    #10;

    // Set inputs and simulate for 8 clock cycles
    a = 8'b00000100;
    b = 8'b00000101;
    #80;

    // End simulation
    $finish;
  end

endmodule

In the above code, a task named addition_task is first defined, which accepts two input parameters and one output parameter. In task we perform the addition of a and b and store the result in a register called sum.

Next, we use the always block in the main logic and call the addition_task inside it. In the testbench, we instantiate the adder module and define the input and output signals. We also set up an initial block to simulate the reset of the module and ended the simulation after simulating some clock cycles.