Verilog common operators, and $display system function ModelSim simulation

Verilog's operators mainly include-
arithmetic operators, Arithmetic Operators
relational operators, Relational Operators
equal operators, Equality Operators
logical operators, Logical Operators
bitwise operators, Bit-wise Operators
reduction operators, Reduction Operators (also called Reduction operator)
shift operator, Shift Operators
conditional operator, Conditional Operators
connection operator, Concatenation Operator
assignment operator, assignment operator;

One, arithmetic operators, Arithmetic Operators

Operator	Description
+	binary plus
-	binary minus
*	multiply
/	divide
+	unary (sign) plus symbolic operator
-	unary (sign) minus symbol operator

Simulation code

module arithmetic_operators();

initial begin
  $display (" 5  +  10 = %d", 5  + 10);
  $display (" 5  -  10 = %d", 5  - 10);
  $display (" 10 -  5  = %d", 10 - 5);
  $display (" 10 *  5  = %d", 10 * 5);
  $display (" 10 /  5  = %d", 10 / 5);
  $display (" 10 /  -5 = %d", 10 / -5);
  $display (" 10 %s  3  = %d","%", 10 % 3);
  $display (" +5       = %d", +5);
  $display (" -5       = %d", -5);
  #10 $finish;
end

endmodule

Simulation:
1. Open modlesim, File-new-source, and enter the code above.

2. Saveas

3. Click compile, find the path where the file was stored just now, and select the file. You will be prompted whether to create a work folder, click Compile first, and then click done.
   

4. Click simulate, in the pop-up serial port, click the plus sign in front of the top work, select the option with the same name as the module, and click OK in the lower right corner.

5. Enter the run command in the transcript serial port below, and a window will pop up to ask you if you want to end it. You must select NO here! Choose yes to exit the program.
   See the result of running $display.
   

Two, relational operators, Relational Operators

The result of the relational operator is 1 or 0, which is true or false.

Operator	Description
a < b	a less than b
a > b	a greater than b
a <= b	a less than or equal to b
a >= b	a greater than or equal to b

Simulation code

module relational_operators();

initial begin
  $display (" 5     <=  10 = %b", (5     <= 10));
  $display (" 5     >=  10 = %b", (5     >= 10));
  $display (" 1'bx  <=  10 = %b", (1'bx  <= 10));
  $display (" 1'bz  <=  10 = %b", (1'bz  <= 10));  
  #10 $finish;
end

endmodule

The simulation steps can refer to the arithmetic operators mentioned above, which is omitted here and only the results are posted.

	
  5     <=  10 = 1
  5     >=  10 = 0
  1'bx  <=  10 = x
  1'bz  <=  10 = x

Three, equality operators, Equality Operators

Operator	Description
a === b	a equal to b, including x and z (Case equality)
a !== b	a not equal to b, including x and z (Case inequality)
a == b	a equal to b, result may be unknown (logical equality)
a != b	a not equal to b, result may be unknown (logical equality)

Simulation code:

module equality_operators();

initial begin
  // Case Equality
  $display (" 4'bx001 ===  4'bx001 = %b", (4'bx001 ===  4'bx001));
  $display (" 4'bx0x1 ===  4'bx001 = %b", (4'bx0x1 ===  4'bx001));
  $display (" 4'bz0x1 ===  4'bz0x1 = %b", (4'bz0x1 ===  4'bz0x1));
  $display (" 4'bz0x1 ===  4'bz001 = %b", (4'bz0x1 ===  4'bz001));
  // Case Inequality
  $display (" 4'bx0x1 !==  4'bx001 = %b", (4'bx0x1 !==  4'bx001));
  $display (" 4'bz0x1 !==  4'bz001 = %b", (4'bz0x1 !==  4'bz001));  
  // Logical Equality
  $display (" 5       ==   10      = %b", (5       ==   10));
  $display (" 5       ==   5       = %b", (5       ==   5));
  // Logical Inequality
  $display (" 5       !=   5       = %b", (5       !=   5));
  $display (" 5       !=   6       = %b", (5       !=   6));
  #10 $finish;
end

endmodule

Simulation results:

Four, logical operators, Logical Operators

Operator	Description
!	logic negation
&&	logical and
||	logical or

Simulation code:

module logical_operators();

initial begin
  // Logical AND
  $display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1));
  $display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0));
  $display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx));
  // Logical OR
  $display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0));
  $display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0));
  $display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx));
  // Logical Negation
  $display ("! 1'b1       = %b", (!  1'b1));
  $display ("! 1'b0       = %b", (!  1'b0));
  #10 $finish;
end

endmodule

Simulation results:

Five, bitwise operators, Bit-wise Operators

Operator	Description
~	negation
&	and
|	inclusive or
^	exclusive or 异或
^~ or ~^	exclusive nor (equivalence)

Bitwise operations are sometimes difficult to observe, especially when multiple operators are together. In order to avoid reading obstacles, use parentheses as much as possible.

Simulation code

module bitwise_operators();

initial begin
  // Bit Wise Negation
  $display (" ~4'b0001           = %b", (~4'b0001));
  $display (" ~4'bx001           = %b", (~4'bx001));
  $display (" ~4'bz001           = %b", (~4'bz001));
  // Bit Wise AND
  $display (" 4'b0001 &  4'b1001 = %b", (4'b0001 &  4'b1001));
  $display (" 4'b1001 &  4'bx001 = %b", (4'b1001 &  4'bx001));
  $display (" 4'b1001 &  4'bz001 = %b", (4'b1001 &  4'bz001));
  // Bit Wise OR
  $display (" 4'b0001 |  4'b1001 = %b", (4'b0001 |  4'b1001));
  $display (" 4'b0001 |  4'bx001 = %b", (4'b0001 |  4'bx001));
  $display (" 4'b0001 |  4'bz001 = %b", (4'b0001 |  4'bz001));
  // Bit Wise XOR
  $display (" 4'b0001 ^  4'b1001 = %b", (4'b0001 ^  4'b1001));
  $display (" 4'b0001 ^  4'bx001 = %b", (4'b0001 ^  4'bx001));
  $display (" 4'b0001 ^  4'bz001 = %b", (4'b0001 ^  4'bz001));
  // Bit Wise XNOR
  $display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001));
  $display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001));
  $display (" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001));
  #10 $finish;
end

endmodule

Simulation results

6. Reduction Operators, Reduction Operators
are also called reduction operators and reduction operators. For this part, please refer to the previous blog post
https://blog.csdn.net/malcolm_110/article/details/90487935

Seven, shift operators, Shift Operators

Operator	Description
<<	left shift
>>	right shift

Simulation code

module shift_operators();

initial begin
  // Left Shift
  $display (" 4'b1001 << 1 = %b", (4'b1001 << 1));
  $display (" 4'b10x1 << 1 = %b", (4'b10x1 << 1));
  $display (" 4'b10z1 << 1 = %b", (4'b10z1 << 1));
  // Right Shift
  $display (" 4'b1001 >> 1 = %b", (4'b1001 >> 1));
  $display (" 4'b10x1 >> 1 = %b", (4'b10x1 >> 1));
  $display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1));
  #10 $finish;
end

endmodule

Simulation results

	
  4'b1001 << 1 = 0010
  4'b10x1 << 1 = 0x10
  4'b10z1 << 1 = 0z10
  4'b1001 >> 1 = 0100
  4'b10x1 >> 1 = 010x
  4'b10z1 >> 1 = 010z

Eight, conditional operators, Conditional Operators

条件操作符就是代码中常见的形式如下的结构
cond_expr ? true_expr : false_expr

Nine, connection operator, Concatenation Operator

The role of the concatenation operator is to achieve bit splicing.

{
    
    a[3:0], 4'b1001}

The result is 8 bits.
There is another type called Replication Operator, which repeats the connection operation, and has the form:
{3{a}} The
effect is equivalent to {a, a, a}

Ten, assignment operator, assignment operator

Operator	Description
=	blocking assignment
<=	Non-blocking assignment

blocking assignment Blocking assignment, used in combinatorial logic, assignment is in no particular order, which may cause competition and risk.
Non-blocking assignment Non-blocking assignment is used in sequential logic. The assignment is in order. For this part, please refer to other materials.