Thanks for sharing the platform-http: //bjbsair.com/2020-04-10/tech-info/53251.html
What is adventure?
Hazard means that in the micro-architecture of the computer CPU, some problems in the out-of-order execution of the instruction pipeline may lead to incorrect calculation results. There are 3 typical risks:
- Data risk
- Structural risk
- Control risk (branch risk)
Give two
Data adventure
When the instructions are executed out of order, the timing and spatial correlation between the read data and the written data may occur, which becomes a data risk. If not dealt with, it may lead to race conditions. There are 3 possible data risks:
- Write before read (RAW), this is the real correlation.
- Read before write (WAR) is called anti-correlation.
- Write after write (WAW) is called output correlation.
Write before read (RAW)
R2 <- R1 + R3.
R4 <- R2 + R3
The implementation on the circuit is as follows: after 600ps, the value of t0 will be saved in the pipeline register of EX / MEM. At the same time, the addition instruction is being executed. It needs to pass the value of t0 to the input of the ALU. Obviously it The value read directly from the t0 register is not the latest. On the latest connection in the memory access phase, we will bring this signal back from the hardware connection as the input terminal of the ALU. Whether to use the pre-delivery signal, we need to control a two-way selector based on whether there is a data hazard.
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When the hardware detects that the source operand of the current instruction is exactly in the EX / MEM pipeline register, it directly passes the value of the EX / MEM register to the input of the ALU instead of reading data from the register file, as shown below: t0 is in EX The stage is calculated, so it can be sent to the input of the next instruction ALU without adding bubbles.
FORWARDING channel
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Separate instruction cache and data cache are provided in the memory. (It should be emphasized that the main memory in the computer, that is, the memory, stores instructions and data uniformly, which is also the requirement of the von Neumann structure, but the first-level cache in the CPU will use the method of storing instructions and data separately)
Set up separate instruction cache and data cache
Although pipeline stalls can be used to solve various adventures, its inefficiency should be avoided as much as possible.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-ANewzmpl-1586505902069) (http://p1.pstatp.com/large/pgc-image/018f470197454a54aedca7f5b305c6c8)]
Add two Cycle waits between these two statements:
We have a convenient and simple method, that is, pipeline stalls, which generate bubbles.
Pipeline pause
How to solve
When an instruction is pipelined, the processor encounters a branch instruction and cannot determine the branch result at the beginning of the pipeline.
Control adventure
Structural risk refers to the fact that multiple instructions simultaneously access a piece of hardware in the processor. A typical example is when a memory unit is fetched operands by one instruction while another instruction writes the result.
Structural adventure
The first instruction is to calculate a value and store it in R2, and the second instruction is to use this value to calculate the result and store it in R4. Not yet saved. So we have a data correlation. We can say that there is a data dependency on instruction i2, which depends on the completion of instruction i1. Thanks for sharing the platform-http: //bjbsair.com/2020-04-10/tech-info/53251.html
What is adventure?
Hazard means that in the micro-architecture of the computer CPU, some problems in the out-of-order execution of the instruction pipeline may lead to incorrect calculation results. There are 3 typical risks:
- Data risk
- Structural risk
- Control risk (branch risk)
Give two
Data adventure
When the instructions are executed out of order, the timing and spatial correlation between the read data and the written data may occur, which becomes a data risk. If not dealt with, it may lead to race conditions. There are 3 possible data risks:
- Write before read (RAW), this is the real correlation.
- Read before write (WAR) is called anti-correlation.
- Write after write (WAW) is called output correlation.
Write before read (RAW)
R2 <- R1 + R3.
R4 <- R2 + R3
The implementation on the circuit is as follows: after 600ps, the value of t0 will be saved in the pipeline register of EX / MEM. At the same time, the addition instruction is being executed. It needs to pass the value of t0 to the input of the ALU. Obviously it The value read directly from the t0 register is not the latest. On the latest connection in the memory access phase, we will bring this signal back from the hardware connection as the input terminal of the ALU. Whether to use the pre-delivery signal, we need to control a two-way selector based on whether there is a data hazard.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-Qv1pfOwQ-1586505902286) (http://p9.pstatp.com/large/pgc-image/fdbfa112ef1a4efca5e1963b367dec12)]
When the hardware detects that the source operand of the current instruction is exactly in the EX / MEM pipeline register, it directly passes the value of the EX / MEM register to the input of the ALU instead of reading data from the register file, as shown below: t0 is in EX The stage is calculated, so it can be sent to the input of the next instruction ALU without adding bubbles.
FORWARDING channel
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-ebyCe42O-1586505902288) (http://p1.pstatp.com/large/pgc-image/e388d6fb8ba04e4c8e4495d0170c8ed4)]
Separate instruction cache and data cache are provided in the memory. (It should be emphasized that the main memory in the computer, that is, the memory, stores instructions and data uniformly, which is also the requirement of the von Neumann structure, but the first-level cache in the CPU will use the method of storing instructions and data separately)
Set up separate instruction cache and data cache
Although pipeline stalls can be used to solve various adventures, its inefficiency should be avoided as much as possible.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-sz847ojq-1586505902290) (http://p1.pstatp.com/large/pgc-image/018f470197454a54aedca7f5b305c6c8)]
Add two Cycle waits between these two statements:
We have a convenient and simple method, that is, pipeline stalls, which generate bubbles.
Pipeline pause
How to solve
When an instruction is pipelined, the processor encounters a branch instruction and cannot determine the branch result at the beginning of the pipeline.
Control adventure
Structural risk refers to the fact that multiple instructions simultaneously access a piece of hardware in the processor. A typical example is when a memory unit is fetched operands by one instruction while another instruction writes the result.
Structural adventure
The first instruction is to calculate a value and store it in R2, and the second instruction is to use this value to calculate the result and store it in R4. Not yet saved. So we have a data correlation. We can say that there is a data dependency on instruction i2, which depends on the completion of instruction i1. Thanks for sharing the platform-http: //bjbsair.com/2020-04-10/tech-info/53251.html
What is adventure?
Hazard means that in the micro-architecture of the computer CPU, some problems in the out-of-order execution of the instruction pipeline may lead to incorrect calculation results. There are 3 typical risks:
- Data risk
- Structural risk
- Control risk (branch risk)
Give two
Data adventure
When the instructions are executed out of order, the timing and spatial correlation between the read data and the written data may occur, which becomes a data risk. If not dealt with, it may lead to race conditions. There are 3 possible data risks:
- Write before read (RAW), this is the real correlation.
- Read before write (WAR) is called anti-correlation.
- Write after write (WAW) is called output correlation.
Write before read (RAW)
R2 <- R1 + R3.
R4 <- R2 + R3
The implementation on the circuit is as follows: after 600ps, the value of t0 will be saved in the pipeline register of EX / MEM. At the same time, the addition instruction is being executed. It needs to pass the value of t0 to the input of the ALU. Obviously it The value read directly from the t0 register is not the latest. On the latest connection in the memory access phase, we will bring this signal back from the hardware connection as the input terminal of the ALU. Whether to use the pre-delivery signal, we need to control a two-way selector based on whether there is a data hazard.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-91tjSQod-1586505902481) (http://p9.pstatp.com/large/pgc-image/fdbfa112ef1a4efca5e1963b367dec12)]
When the hardware detects that the source operand of the current instruction is exactly in the EX / MEM pipeline register, it directly passes the value of the EX / MEM register to the input of the ALU instead of reading data from the register file, as shown below: t0 is in EX The stage is calculated, so it can be sent to the input of the next instruction ALU without adding bubbles.
FORWARDING channel
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-27j4FKD8-1586505902483) (http://p1.pstatp.com/large/pgc-image/e388d6fb8ba04e4c8e4495d0170c8ed4)
Separate instruction cache and data cache are provided in the memory. (It should be emphasized that the main memory in the computer, that is, the memory, stores instructions and data uniformly, which is also the requirement of the von Neumann structure, but the first-level cache in the CPU will use the method of storing instructions and data separately)
Set up separate instruction cache and data cache
Although pipeline stalls can be used to solve various adventures, its inefficiency should be avoided as much as possible.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-Rw4uHChY-1586505902485) (http://p1.pstatp.com/large/pgc-image/018f470197454a54aedca7f5b305c6c8)]
Add two Cycle waits between these two statements:
We have a convenient and simple method, that is, pipeline stalls, which generate bubbles.
Pipeline pause
How to solve
When an instruction is pipelined, the processor encounters a branch instruction and cannot determine the branch result at the beginning of the pipeline.
Control adventure
Structural risk refers to the fact that multiple instructions simultaneously access a piece of hardware in the processor. A typical example is when a memory unit is fetched operands by one instruction while another instruction writes the result.
Structural adventure
The first instruction is to calculate a value and store it in R2, and the second instruction is to use this value to calculate the result and store it in R4. Not yet saved. So we have a data correlation. We can say that there is a data dependency on instruction i2, which depends on the completion of instruction i1. Thanks for sharing the platform-http: //bjbsair.com/2020-04-10/tech-info/53251.html
What is adventure?
Hazard means that in the micro-architecture of the computer CPU, some problems in the out-of-order execution of the instruction pipeline may lead to incorrect calculation results. There are 3 typical risks:
- Data risk
- Structural risk
- Control risk (branch risk)
Give two
Data adventure
When the instructions are executed out of order, the timing and spatial correlation between the read data and the written data may occur, which becomes a data risk. If not dealt with, it may lead to race conditions. There are 3 possible data risks:
- Write before read (RAW), this is the real correlation.
- Read before write (WAR) is called anti-correlation.
- Write after write (WAW) is called output correlation.
Write before read (RAW)
R2 <- R1 + R3.
R4 <- R2 + R3
The implementation on the circuit is as follows: after 600ps, the value of t0 will be saved in the pipeline register of EX / MEM. At the same time, the addition instruction is being executed. It needs to pass the value of t0 to the input of the ALU. Obviously it The value read directly from the t0 register is not the latest. On the latest connection in the memory access phase, we will bring this signal back from the hardware connection as the input terminal of the ALU. Whether to use the pre-delivery signal, we need to control a two-way selector based on whether there is a data hazard.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-89Lc7rf3-1586505902678) (http://p9.pstatp.com/large/pgc-image/fdbfa112ef1a4efca5e1963b367dec12)]
When the hardware detects that the source operand of the current instruction is exactly in the EX / MEM pipeline register, it directly passes the value of the EX / MEM register to the input of the ALU instead of reading data from the register file, as shown below: t0 is in EX The stage is calculated, so it can be sent to the input of the next instruction ALU without adding bubbles.
FORWARDING channel
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-qZ6oA4lE-1586505902680) (http://p1.pstatp.com/large/pgc-image/e388d6fb8ba04e4c8e4495d0170c8ed4)]
Separate instruction cache and data cache are provided in the memory. (It should be emphasized that the main memory in the computer, that is, the memory, stores instructions and data uniformly, which is also the requirement of the von Neumann structure, but the first-level cache in the CPU will use the method of storing instructions and data separately)
Set up separate instruction cache and data cache
Although pipeline stalls can be used to solve various adventures, its inefficiency should be avoided as much as possible.
[External chain image transfer failed, the source site may have an anti-theft chain mechanism, it is recommended to save the image and upload it directly (img-T1YJX6IT-1586505902683) (http://p1.pstatp.com/large/pgc-image/018f470197454a54aedca7f5b305c6c8)]
Add two Cycle waits between these two statements:
We have a convenient and simple method, that is, pipeline stalls, which generate bubbles.
Pipeline pause
How to solve
When an instruction is pipelined, the processor encounters a branch instruction and cannot determine the branch result at the beginning of the pipeline.
Control adventure
Structural risk refers to the fact that multiple instructions simultaneously access a piece of hardware in the processor. A typical example is when a memory unit is fetched operands by one instruction while another instruction writes the result.
Structural adventure
The first instruction is to calculate a value and store it in R2, and the second instruction is to use this value to calculate the result and store it in R4, but when we take out the operand of the second step, the result of the first step Not yet saved. So we have a data correlation. We can say that there is a data dependency on instruction i2, which depends on the completion of instruction i1.
