1. Project creation under project
#generate.tcl脚本中的目录可以自行更改
set device xc7z045
set package fbg676
set speed -1
set part $device$package$speed
set prjName xxxxx
set prjDir ./$prjName
set srcDir ./Source
create_project $prjName $prjDir -part $part
add_files [glob $srcDir/hdl/*.v]
add_files [glob $srcDir/hdl/*.vh]
add_files [glob $srcDir/ip/*.xcix]
updata_complie_order -fileset sources_1
addfiles -fileset constrs_1 [glob $srcDir/xdc/*.xdc]
addfiles -fileset sim_1 [glob $srcDir/tb/*.v]
updata_complie_order -fileset sim_1
set_property strategy Flow_AreaOptimized_high [get_runs srnth_1]
set_property strategy Performance_Explore [get_runs impl_1]
launch_runs synth_1
wait_on_run synth_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
start_gui
#生成固化文件的方法
write_cfgmem -format mcs -interface SPIx4 -size 128 -loadbit {
up 0x0 路径.bit} -file 路径.mcs
#如果你只是想创建工程文件，然后自己添加还没写的.v文件
set device xc7z045
set package fbg676
set speed -1
set part $device$package$speed
set prjName xxxxx
set prjDir ./$prjName
set srcDir ./Source
create_project $prjName $prjDir -part $part
file mkdir $prjDir/$prjName.srcs/sources_1/new
set fid [open $prjDir/$prjName..srcs/sources_1/new/xxx.v w]
close $fid
add_files $prjDir/$prjName.srcs.srcs/sources_1/new/xxx.v
#删除文件
file delete -force ddr_nn1.v
export_ip_user_files -of_objects [get_files F:/FPGA/DDRTEST/DDRTEST.srcs/sources_1/new/ddr_nn1.v] -no_script -reset -force -quiet
remove_files F:/FPGA/DDRTEST/DDRTEST.srcs/sources_1/new/ddr_nn1.v
2.Hook script
The implementation phase of vivado has the following steps
1. Design initialization phase init_design
2. Design optimization opt_design is executed by default
3. Power consumption optimization power_opt_design
4. Layout place_design is executed by default
5. Post-layout power consumption optimization power_opt_design (post_place_power_opt_design)
6. Post-layout physical optimization phys_opt_design is executed by default
7. Routing route_design is executed by default
8. Post-routing physical optimization post_route_phys_opt_design
Then the hook script properties in the synthesis phase are
SET.SYNTH_DESIGN.TCL.PRE
SET.SYNTH_DESIGN.TCL.POST
. The hook script properties in the implementation phase are
SET.INIT_DESIGN.TCL.PRE
SET.INIT_DESIGN.TCL.POST
SET.OPY_DESIGN.TCL.PRE
SET.OPT_DESIGN.TCL.POST
can be found to be the capital letters of each step in the implementation phase, so we will not expand and write them one by one. The
complete operation is as follows:
set_property SET.SYNTH_DESIGN.TCL.POST [get_files C:/report0.tcl -of [get_fileset utils_1 ]] [get_runs synth_1]
Among them, get_files C:/report0.tcl -of [get_fileset utils_1] means to get the C:/report0.tcl file under utils_1
3.Non-Project mode
The design process is as follows:
1. Set basic parameters
2. Read in the design source file
3. Perform OOC comprehensive operation on the IP
4. Perform comprehensive operation on the entire design
5. Execute each sub-step of the implementation phase
6. Generate bit stream file
1Set basic parameters
#与Prioject模式很相似 run_v1.tcl
set device xc7z045
set package fbg676
set speed -1
set part $device$package$speed
set top wave_gen
set srcDir ./Source
set SynOutputDir ./SynOutputDir
set ImplOutputDir ./ImplOutputDir
set synDirective Default
set optDirective Default
set placeDirective Default
set phys0ptDirectiveAp Default
set routeDirective Default
set phys0ptDirectiveAr Default
set_param general.maxThreads 6
source run_read_src_v1.tcl
source run_synth_ip_v1.tcl
source run_synth_v1.tcl
source run_impl_v1.tcl
source run_bitstream_v1.tcl
2. Read in the design source file
#run_read_src_v1.tcl
read_verilog [glob $srcDir/hdl/*.v]
read_verilog [glob $srcDir/hdl/*.vh]
read_edlf [glob $srcDir/netlist/*.edn]
read_ip [glob $srcDir/ip/*.xcix]
read_xdc [glob $srcDir/xdc/*.xdc]
link_design -top $top -part $part
3. Perform OOC comprehensive operations on IP
#run_synth_ip_v1.tcl
synth_ip [get_ips]
#synth_ip [get_ips chara-fifo]
#synth_ip [get_ips clk_core]
#表示只对指定IP进行ooc综合（out_of_context）
4. Comprehensive operation of the entire design
#run_synth_v1.tcl
synth_design -top $top -part $part -directive default
#top 指定顶层文件名 part指定FPGA型号 directive指定指令，这里是默认
write_checkpoint -force $SynOutputDir/post_synth
#这里创建了post_synth.dcp文件，并且覆盖了原有的post_synth.dcp文件
report_timing_summary -file $SynOutputDir/post_synth_timing_summary.rpt
report_utilization -file $SynOutputDir/post_synth_util.rpt
#生成了时序报告和资源利用率报告
5. Execute various sub-steps of the implementation phase
#run_impl_v1.tcl
#根据默认执行步骤，首先执行的是设计优化
opt_design -directive $optDirective
write_checkpoint -force $ImplOutputDir/post_opt
report_timing_summary -file $ImplOutputDir/post_opt_timing_summary.rpt
report_utilization -file $ImplOutputDir/post_opt_util.rpt
#然后是布局、布局后物理优化、布线，只需将上面的opt改为place phys_opt route即可，不一一写出
6. Generate bitstream file
#run_bitstream_v1.tcl
set_porperty CONFIG_MODE SPIx4 [current_design]
set_porperty BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
write_ bitstream -verbose -force -bin_file $ImplOutputDir/top.bit
#设置QSPI为四线模式，66MHz，同时生成.bin和.bit文件
7. Save the log file to the specified file
opt_design -directive Default > ./chech_opt.log
place_design -directive Default > ./chech_place.log
phys_design -directive Default > ./chech_phys.log
route_design -directive Default > ./chech_route.log
8. Calculate the elapsed value
set start_time [clock format [clock seconds] -format "%s"]
place_design
set end_time [clock format [clock seconds] -format "%s"]
set place_elapse [clock format [expr $end_time - $start_time] -format "%H:%M:%S" -gmt true]
4. Scanning strategy
The scan strategy is a timing closure method. Scanning strategies are divided into scanning comprehensive strategies and scanning implementation strategies. In most cases, a scanning implementation strategy is more effective.
Scanning implementation strategies actually scans different -directive values.
In Non-Project mode, there are usually 5 scanning methods:
模式0：只扫描place_design的-directive值（此时需要提供opt_design生成的.dcp）
模式1：只扫描route_design的-directive值（此时需要提供place_design生成的.dcp）
模式2：顺序扫描方式，即先提供place_design、phys_opt_design、route_design的-directive组合，然后进行扫描
模式3：先扫描place_design下的-directive值，从中获取WNS最好的情形，然后执行phys_opt_design,并在此基础上，扫描route_design的-directive值
模式4：交织扫描方式，即每一个place_design的-directive值和route_design的-directive值构成一个扫描对
Get the commands for WNS and WHS:
set tps [get_timing_paths -max_paths 100 -setup]
set wns [get_property SLACK [lindex $tps 0]]
set tph [get_timing_paths -max_paths 100 -hold]
set whs [get_property SLACK [lindex $tph 0]]