- The registers in ARM include SFR and 37 general-purpose registers, and the general-purpose registers are an integral part of the CPU (calculator + controller + general-purpose registers).
- 37 general-purpose registers are learned with 7 working modes. Because the visible general-purpose registers are different in each working mode, you can only see up to 18 registers in each mode, and some registers have the same name, but they are not visible in the current mode.
- For the name R13, there are 6 registers named R13 (also called sp) in ARM, but in each specific working mode, only the R13 of the current mode is visible, and other r13 must be switched to other corresponding modes to see it. This design is called a shadow deposit (banked register).
- The user mode and the system mode share a set of registers, and the five abnormal modes have their own R13, R14 and SPSR.
- R13 is used as a stack pointer, so it is also called sp; since each operating mode of the processor has its own independent physical register R13, in the initialization part of the user application program, it is generally necessary to initialize R13 in each mode to point to Stack space for this run mode. In this way, when the operation of the program enters the exception mode, the registers to be protected can be put into the stack pointed to by R13, and when the program returns from the exception mode, it is restored from the corresponding stack. This method can ensure that the exception occurs After the normal execution of the program.
- R14 is used to save the return address, so it is also called the link register lr; when the subroutine call instruction (BL) is executed, R14 can get the backup of R15 (program counter PC). In each operating mode, R14 can be used to save the return address of the subroutine. When the subroutine is called by the BL or BLX instruction, the current value of the PC is copied to R14. After the subroutine is executed, the value of R14 is copied. Return to the PC to complete the subroutine call and return.
- r15 is used as a program control register, so it is also called PC; in ARM state, bits [1:0] are 0, bits [31:2] are used to save PC, in Thumb state, bits [0] are 0, bits [31:1] is used to save the PC. Since the ARM architecture adopts multi-stage pipeline technology, for the ARM instruction set, the PC always points to the address of the next two instructions of the current instruction, that is, the value of the PC is the address value of the current instruction plus 8 bytes.
- CPSR Program Status Register. Record the state of the current CPU; CPSR can be accessed in any operating mode, which includes condition flag bits, interrupt disable bits, current processor mode flag bits, and other related control and status bits.
- SPSR is a replication of CPSR. Each operating mode has a dedicated physical status register, called SPSR (Saved Program Status Register, backup program status register). When an exception occurs, SPSR is used to save the current value of CPSR. When exiting from an exception The CPSR can then be recovered by the SPSR.
Since user mode and system mode are not exception modes, they do not have SPSR, when accessing SPSR in these two modes, the result is unknown.
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