what is abnormal
Processes other than normal work are called exceptions
Exceptions will interrupt the work being performed, and generally we want to continue to perform the original work after the exception is handled
Interrupts are a type of exception
exception vector table
All CPUs have an exception vector table, which is set when the CPU is designed and is determined by the hardware.
When an exception occurs, the CPU will automatically act (the PC jumps to the exception vector to handle the exception, sometimes accompanied by some auxiliary actions)
The exception vector table is the support provided by the hardware to the software for handling exceptions.
ARM exception handling mechanism
When an exception occurs, the ARM core:
(1) Save the value of CPSR to the SPSR corresponding to the abnormal interrupt to be executed, so as to realize the protection of the current state of the processor, the interrupt mask and each flag bit.
(2) Set the corresponding bit of the current state register CPSR. Set the 5 bits of M4~M0 in CPSR to enter the corresponding working mode, set I=1 to disable the IRQ interrupt, if entering the reset mode or FIQ mode, also set F=1 to disable the FIQ interrupt.
(3) Save the next address (breakpoint address) of the instruction that caused the exception to LR (R14), so that after the exception handler is executed, it will return to the original program and continue to execute downward.
(4) Mandatory assignment to the program counter PC, transfer to the vector address, so as to execute the corresponding processing program.
Each interrupt exception mode corresponds to two registers SP and LR.
Return from interrupt. If it is a reset exception, the system automatically re-executes the program from 0x00000000 without returning
(1) First restore the original protected user registers.
(2) Copy the SPSR register to the CPSR, so that the original CPSR state is restored from the corresponding SPSR,—resume the interrupted program state.
(3) Restoring the PC value to the breakpoint address according to the exception type, so as to continue to execute the program originally running by the user.
(4) Clear the interrupt prohibition flags I and F in the CPSR, and open external interrupts and fast interrupts.
Notice:
(1) Restoration of program status register and breakpoint address must be carried out simultaneously.
(2) Because the exception occurs randomly, the exception vector needs to be initialized, that is, a jump instruction is placed at the address of the exception vector to jump to the exception handler.
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