In the article "PCB Design 丨 The Importance of Power Supply Design", the general requirements of power supply design and related knowledge points such as layout and wiring of different circuits have been introduced. In this article, the editor will take RK3588 as an example to give you a detailed introduction . Introduce the PCB design of other branch power supplies.
Power PCB design
VDD_CPU_BIG0/1
01
The filter capacitor shown in the figure below (above), the decoupling capacitor close to the green line of the VDD_CPU_BIG power pin of RK3588 on the schematic diagram must be placed on the back of the corresponding power pin, and the capacitor GND PAD should be as close as possible to the GND pin in the center of the chip Place as shown in the following figure (bottom).
The rest of the decoupling capacitors should be placed near the chip as much as possible, and they need to be placed on the path of the power split source.
02
The power supply pins of RK3588 chip VDD_CPU_BIG0/1 ensure that there is a corresponding via hole on the side of each pin, and the top layer is in a "well" shape, cross-connected.
The figure below shows the fan-out wiring of the power pins. The recommended wiring width is 10mil.
03
The width of the VDD_CPU_BIG0/1 copper pour should meet the current demand of the chip, and the copper pour width connected to the power pin of the chip should be sufficient.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the paths connected to each power PIN of the CPU are sufficient.
04
When the VDD_CPU_BIG power supply changes layers at the periphery, it is necessary to drill as many power supply vias as possible (12 or more 0.5*0.3mm vias) to reduce the voltage drop caused by the layer-changing vias.
The GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced.
05
The relatively large VDD_CPU_BIG current requires double-layer copper pouring. The total line width of the VDD_CPU_BIG power supply in the CPU area should not be less than 300mil, and the width of the peripheral area should not be less than 600mil.
Try to use copper pouring to reduce the voltage drop caused by the wiring (please do not place other signal layer-changing vias randomly, they must be placed regularly, and try to make room for the power supply, which is also conducive to the copper pouring of the ground layer), as shown in the figure below.
06
The power plane will be damaged by the anti-pad of the via hole. When designing the PCB, pay attention to adjusting the positions of other signal vias so that the effective width of the power supply meets the requirements.
The L1 in the figure below shows that the width of the copper skin of the power supply is 58mil. Since the anti-pad of the via hole will damage the copper skin, the actual effective overcurrent width is only L2+L3+L4=14.5mil.
07
The number of GND vias within the 40mil range of the BIG0/1 power supply vias (the distance from the center of the via to the center of the via) is recommended to be ≧12, as shown in the figure below.
08
The recommended value of the PDN target impedance of the BIG power supply is shown in the table and figure below.
Power PCB design
VDD_LOGIC
01
The copper pour width of VDD_LOGIC needs to meet the current demand of the chip, and the copper pour connected to the power pin of the chip is wide enough.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the paths connected to each power PIN of the CPU are sufficient.
02
As shown in the figure below (above), the decoupling capacitor within the green line close to the VDD_LOGIC power pin of the RK3588 on the schematic diagram must be placed on the back of the corresponding power pin, and the GND pin of the capacitor should be placed as close to the GND pin in the center of the chip as possible. , as shown in the figure below (bottom).
The rest of the decoupling capacitors should be placed near the RK3588 chip as much as possible, and placed on the path of the power split source.
03
The power supply pins of RK3588 chip VDD_LOGIC, each pin needs to correspond to a via hole, and the top layer is in the shape of a "well", cross-connected, as shown in the figure below, the recommended line width is 10mil.
04
BIG0/1 power supply via hole 40mil range (the line width of the VDD_LOGIC power supply in the CPU area between the center of the via hole and the center of the via hole should not be less than 120mil, and the width of the peripheral area should not be less than 200mil.
Try to use the copper pour method to reduce the voltage drop caused by the wiring (please do not place other signal layer-changing vias randomly, they must be placed regularly, try to make room for the power supply, and it is also conducive to the copper pouring of the ground layer), the number of GND via holes is recommended ≧12.
05
When the power supply of VDD_LOGIC changes layers at the periphery, it is necessary to drill as many power supply vias as possible (more than 8 vias of 10-20mil) to reduce the voltage drop caused by layer-changing vias.
The number of GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced, as shown in the figure below.
06
The number of GND vias within the 40mil range of the power vias (the distance from the center of the via to the center of the via) is recommended to be ≧11, as shown in the figure below.
Power PCB design
VDD_GPU
01
The copper pour width of VDD_GPU needs to meet the current demand of the chip, and the copper pour connected to the power pin of the chip is wide enough.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the path connected to each power PIN of the CPU is sufficient.
02
When the VDD_GPU power supply is changing layers at the periphery, it is necessary to drill as many power supply vias as possible (more than 10 vias of 0.5*0.3mm) to reduce the voltage drop caused by the layer-changing vias.
The GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced.
03
As shown in the figure below (above), the decoupling capacitor within the green line close to the VDD_GPU power pin of the RK3588 on the schematic diagram must be placed on the back of the corresponding power pin, and the GND PAD of the capacitor should be placed as close as possible to the GND pin in the center of the chip, as follows Figure (below) shows.
The rest of the decoupling capacitors should be placed near the RK3588 chip as much as possible, and should be placed on the path of the power split source.
04
For the power supply pins of RK3588 chip VDD_GPU, each pin needs to correspond to a via hole, and the top layer is in a "well" shape, cross-connected, as shown in the figure below, and the recommended line width is 10mil.
05
The line width of the VDD_GPU power supply in the GPU area shall not be less than 300mil, and the width of the peripheral area shall not be less than 500mil. The two-layer copper clad method is used to reduce the voltage drop caused by the wiring.
06
The number of GND vias within the 40mil range of the power vias (the distance from the center of the via to the center of the via) is recommended to be ≧14, as shown in the figure below.
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Power PCB design
VDD_NPU
01
The copper pour width of VDD_NPU needs to meet the current demand of the chip, and the copper pour connected to the power pin of the chip is wide enough.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the path connected to each power PIN of the CPU is sufficient.
02
When the power supply of VDD_NPU changes layers at the periphery, it is necessary to drill as many power supply vias as possible (more than 7 vias of 0.5*0.3mm) to reduce the voltage drop caused by layer-changing vias.
The GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced.
03
As shown in the figure below (above), the decoupling capacitor within the green line of the VDD_NPU power pin of the RK3588 on the schematic diagram must be placed on the back of the corresponding power pin, and the GND PAD of the capacitor should be placed as close as possible to the GND pin in the center of the chip, as follows Figure (below) shows.
The rest of the decoupling capacitors should be placed near the RK3588 chip as much as possible, and should be placed on the path of the power split source.
04
The power supply pin of RK3588 chip VDD_NPU, each pin has a corresponding via hole nearby, and the top layer is in a "well" shape, cross-connected, as shown in the figure below, the recommended line width is 10mil.
05
The line width of the VDD_NPU power supply in the NPU area shall not be less than 300mil, and the width of the peripheral area shall not be less than 500mil.
Try to use copper pouring method to reduce the voltage drop caused by the wiring (please do not place other signal layer-changing vias randomly, but must be placed regularly, try to make room for the power supply, and it is also conducive to the copper pouring of the ground).
06
The number of GND vias within the 40mil range of the power vias (the distance from the center of the via to the center of the via) is recommended to be ≧9.
Power PCB design
VDD_CPU_LIT
01
The copper pour width of VDD_CPU_LIT needs to meet the current demand of the chip, and the copper pour connected to the power pin of the chip is wide enough.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the path connected to each power PIN of the CPU is sufficient.
02
When the VDD_CPU_LIT power supply changes layers at the periphery, it is necessary to drill as many power supply vias as possible (9 or more 0.5*0.3mm vias) to reduce the voltage drop caused by the layer-changing vias.
The GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced.
03
As shown in the figure below (above), the decoupling capacitor within the green line close to the VDD_CPU_LIT power pin of RK3588 on the schematic diagram must be placed on the back of the corresponding power pin, and the GND PAD of the capacitor should be placed as close as possible to the GND pin in the center of the chip, as follows Figure (below) shows.
The rest of the decoupling capacitors should be placed near the RK3588 chip as much as possible, and should be placed on the path of the power split source.
04
For the power supply pins of RK3588 chip VDD_CPU_LIT, each pin has a corresponding via hole nearby, and the top layer is in the shape of a "well" and cross-connected. The recommended wiring width is 10mil as shown in the figure below.
05
The line width of the VDD_CPU_LIT power supply in the CPU area shall not be less than 120mil, and the width of the peripheral area shall not be less than 300mil.
The double-layer power supply copper pour method is adopted to reduce the voltage drop caused by the wiring (please do not place other signal layer-changing vias randomly, but must be placed regularly, and try to make room for the power supply, which is also conducive to the copper pouring of the ground).
06
The number of GND vias within the 40mil range of the power vias (the distance from the center of the via to the center of the via) is recommended to be ≧9.
Power PCB design
VDD_VDENC
01
The copper pour width of VDD_VDENC needs to meet the current demand of the chip, and the copper pour connected to the power pin of the chip is wide enough.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the path connected to each power PIN of the CPU is sufficient.
02
When the VDD_VDENC power supply changes layers at the periphery, it is necessary to drill as many power supply vias as possible (more than 9 vias of 0.5*0.3mm) to reduce the voltage drop caused by the layer-changing vias.
The GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced.
03
As shown in the figure below (above), the decoupling capacitor within the green line close to the VDD_VDENC power pin of the RK3588 on the schematic diagram must be placed on the back of the corresponding power pin, and the GND PAD of the capacitor should be placed as close as possible to the GND pin in the center of the chip, as follows Figure (below) shows.
The rest of the decoupling capacitors should be placed near the RK3588 chip as much as possible, and should be placed on the path of the power split source.
04
The power supply pin of RK3588 chip VDD_VDENC, each pin has a corresponding via hole nearby, and the top layer is in a "well" shape, cross-connected, as shown in the figure below, the recommended line width is 10mil.
05
The line width of the VDD_VDENC power supply in the CPU area shall not be less than 100mil, and the width of the peripheral area shall not be less than 300mil. The double-layer power supply copper clad method is adopted to reduce the voltage drop caused by the wiring.
06
The number of GND vias within the 30mil range of the power vias (the distance from the center of the via to the center of the via) is recommended to be ≧8.
Power PCB design
VCC_DDR
01
The width of the VCC_DDR copper pour needs to meet the current demand of the chip, and the copper pour connected to the power pin of the chip is wide enough.
The path cannot be divided too severely by vias, and the effective line width must be calculated to confirm that the path connected to each power PIN of the CPU is sufficient.
02
When the VCC_DDR power supply changes layers at the periphery, it is necessary to drill as many power supply vias as possible (more than 9 vias of 0.5*0.3mm) to reduce the voltage drop caused by the layer-changing vias.
The GND vias of the decoupling capacitor should be consistent with the number of its power vias, otherwise the capacitive effect will be greatly reduced.
03
As shown in the figure below (above), the decoupling capacitor close to the VCC_DDR power pin of the RK3588 on the schematic diagram must be placed on the back of the corresponding power pin. The GND PAD of the capacitor should be placed as close as possible to the GND pin in the center of the chip, and the rest The capacitor should be as close as possible to the RK3588, as shown in the figure below (bottom).
04
For the power supply pins of the RK3588 chip VCC_DDR, each pin needs to correspond to a via hole, and the top layer is in the shape of a "well" and cross-connected. The recommended wiring width is 10mil as shown in the figure below.
When LPDDR4x is used, the link method is shown in the figure below.
05
The line width of the VCC_DDR power supply in the CPU area shall not be less than 120mil, and the width of the peripheral area shall not be less than 200mil.
Try to use the copper pouring method to reduce the voltage drop caused by the wiring (please do not place other signal layer-changing vias randomly, but must be placed regularly, try to make room for the power supply, and it is also conducive to the copper pouring of the ground).
