2 Features and basic concepts of SPI
3.1 SPI controller internal registers
3.2 Clock Polarity (CPOL) and Clock Phase (CPHA)
4.1 W25Q256JV--SPI communication FLASH, Winbond
4.2 SC18IS602B, IIC to SPI chip--NXP
5 SPI information and chip selection recommendation
SPI hardware circuit design
1 Introduction to SPI
SPI is the abbreviation of Serial Peripheral Interface (Serial Peripheral Interface). It is a synchronous serial transmission specification first introduced by Motorola . , full-duplex, synchronous communication bus , so data can be sent and received at the same time. SPI does not define a speed limit, usually it can reach 10-100M/bps.
SPI has two modes, master and slave , and usually consists of a master module and one or more slave modules (SPI does not support multi-master) , and the master module selects a slave module for synchronous communication to complete data exchange. The master device (Master) that provides the clock, the device that receives the clock is the slave device (Slave), and the data transmission of the SPI interface (reading and writing operations for FLASH) is initiated by the master device. When there are multiple slave devices , managed by their respective chip select signals.
The standard SPI communication interface consists of the following four lines:
MISO (Master Input Slave Output): master device data input, slave device data output;
MOSI (Master Output Slave Input): master device data output, slave device data input;
SCLK (Serial Clock): clock signal, generated by the master device;
CS/SS/NSS (Chip Select/Slave Select): slave device enable signal , controlled by the master device, when one master has multiple slaves, CS/SS is the control signal whether the slave chip is selected by the master chip , only the chip select signal is When the pre-specified enable signal (high level or low level, find the slave device Datasheet ), the operation of the master chip on this slave chip is valid.
2 Features and basic concepts of SPI
2.1 Features of SPI
(1) Master mode and slave mode
(2) High-speed, full-duplex, synchronous communication
(3) Bidirectional mode, 3-wire SPI, Dual SPI, Qual SPI (QSPI)
(4) When there are multiple slaves, the slave selects the output
(5) Mode error flag, multi-master error reporting, CPU interrupt function
(6) Bidirectional data buffer register, shift register
(7) Programmable clock polarity (CPOL/CKP) and clock phase (CPHA/CKE)
(8) Control of SPI in wait mode, wait mode is a configurable low power mode
2.2 The basic concept of SPI
2.2.1 SPI bus terms
SS/CS：Slave Select
SCK：Serial Clock
MOSI：Master Output, Slave Input
MISO：Master Input, Slave Output
MOMI：Master Output, Master Input
SISO：Slave Input, Slave Output
2.2.2 SPI controller internal structure block diagram
The main parts of the SPI are status, control and data registers , shifter logic , baud rate generator , master/slave control logic, and port control logic . This structure is the structure of the Motorola protocol, and the internal SPI structure of each main controller may be slightly different.
2.2.3 Running status of SPI bus
SPI has three modes, namely run, wait and stop.
Run Mode : This is the most basic mode of operation.
Wait Mode : SPI operation in wait mode is a configurable low-power mode controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is cleared, the SPI enters run mode. If the SPISWAI bit is set, the SPI will enter a power conservative state and SPI clock generation will be turned off . If the SPI is configured as a master, any ongoing transfers will be stopped, but resumed after the CPU enters run mode. If the SPI is configured as a slave, the reception and transmission of bytes continues so that the slave remains in sync with the master.
Stop Mode: The SPI is inactive in Stop Mode to reduce power consumption. If the SPI is configured as a master, any ongoing transfers will be stopped, but resumed after the CPU enters run mode. If the SPI is configured as a slave, the reception and transmission of bytes continues so that the slave remains in sync with the master.
For a more detailed description, see the protocol document, just a general understanding.
2.2.4 The difference between standard SPI and 3-wire SPI, Dual SPI and Qual SPI (6-wire)
(1) Standard SPI: Standard SPI is usually called SPI, and has 4 pin signals: clk, cs, mosi, miso.
(2) 3-wire SPI: When setting the SPC0 bit in the SPI control register 2, select the bidirectional mode. In this mode, SPI uses only one serial data pin. The MSTR bit determines which pin is used . The MOSI pin becomes the master-mode serial data I/O (MOMI) pin , and the MISO pin becomes the slave-mode serial data I/O (SISO) pin . SPI does not use the MISO pin in master mode and the MOSI pin in slave mode. Therefore, the three-wire SPI contains 3 signal lines, CLK, CS, MOMI (SOSI). Motorola's 3-wire SPI has CS, and the data line becomes bidirectional.
TI's 3-wire SPI has no CS signal, uses CLK, MOSI, MISO, and cannot be operated from multiple slaves. And it shows that 2-wire unidirectional operation is not supported, that is, only CLK and MOSI or MISO are used.
(3) Dual SPI (Dual serial peripheral interface) two-wire serial peripheral interface
Dual SPI is generally for SPI Flash, not all SPI peripherals support this mode. For SPI Flash, full-duplex is not commonly used, so the usage of mosi and miso is expanded to allow them to work in half-duplex to double data transmission. That is to say, for Dual SPI Flash, you can send a command byte to enter dual mode, so that mosi becomes SIO0 (serial io 0), and miso becomes SIO1 (serial io 1), so that 2 bits of data can be transmitted within one clock cycle , doubling the data transfer . Only works in half duplex.
(4) Qual SPI (Quad serial peripheral interface) 4 and data lines
Similar to D ual SPI, but also for SPI Flash, Qual SPI Flash adds two I/O lines (SIO2 (WP), SIO3 (HOLD)), the purpose is to transmit 4 bits within one clock.
So for SPI Flash, there are three working modes: standard spi flash, dual spi, and qual spi. It can work with 3-wire, 4-wire, and 6-wire. Under the same clock, the more wires, the higher the transmission rate.