2.3.3 SPI
The SPI (Serial Peripheral Interface, Serial Peripheral Interface) bus system is a synchronous serial peripheral interface that enables the CPU to communicate with various peripheral devices in a serial manner to exchange information. Generally, the master SoC acts as the "master" of the SPI, and the peripherals act as the "slave" of the SPI.
The SPI interface generally uses 4 lines: CS (chip select signal), serial clock line (SCLK), master input/slave output data line MISO and master output/slave input data line MOSI. Figure 2.12 shows the hardware connection diagram of 1 host (master) connecting 3 SPI peripherals (slave).
Figure 2.12 SPI master and slave hardware connection diagram
As shown in Figure 2.13, the SPI bus timing.
Figure 2.13 Timing of SPI bus
In the transmission of the SPI bus, the CS signal is active low. When we want to communicate with a peripheral, we need to set the CS line on the peripheral to low. In addition, pay special attention to the highest clock frequency of the SPI bus supported by the SPI slave device (which determines the frequency of SCK) and the CPHA (clock phase) and CPOL (clock polarity) modes of the peripherals. This determines the skew between the data and the clock, the timing of the sampling, and whether the triggering edge is a rising or falling edge.
In order to exchange data with the peripherals, the SPI module can configure the output serial synchronous clock polarity (CPOL) and phase (CPHA) according to the working requirements of the peripherals.
If CPOL=0, the idle state of the serial sync clock is low; if CPOL=1, the idle state of the serial sync clock is high.
If CPHA=0, data is sampled on the first transition edge (rising or falling) of the serial sync clock; if CPHA=1, data is sampled on the second transition edge (rising or falling) of the serial sync clock sampling.