SPI protocol
SPI is a synchronous serial communication interface.
SPI Serial Peripheral Interface English is the abbreviation of the name suggests is a serial peripheral interface. SPI is a high-speed, full-duplex, synchronous communication bus standard SPI also uses only four pins, it is commonly used in communications devices and microcontroller EEPROM, FLASH, real-time clock, a digital signal processor or the like. SPI communication principle simpler than I2C, it is primarily master-slave communication mode, this mode is typically only one host and one or more slave SPI standard is four lines are the SSEL (chip select, also written SCS) , the SCLK (clock, also written SCK), MOSI (master Out slave input master output / slave input) and MISO (master In slave Out master input / slave output).
SSEL: enable signal from the device chip. If the device is enabled, then a low level, when the pin is pulled low, the device will be selected from the host, and the selected slave from communication.
SCLK: clock signal generated by the host, and the SCL I2C communication somewhat similar.
MOSI: send commands to the master or the slave data channel.
MISO: passage from the host reads data, or state machine.
In some cases, we may also communicate with the SPI or SPI 2 lines of three lines. For example, only to be sent from the host machine command, from the time machine does not need to return data that MISO can not; but only reads data from the host machine, no time to send instructions from the machine, it may not MOSI; when a host from a machine when the machine is selected from may be fixed to the active level and has been in an enabled state, it can not SSEL; case only if coupled to a host sends data, and then SSEL MISO can not; if the host only reads the data sent from the machine, SSEL and MOSI are not. 3-wire and SPI 2 lines you want to know how it is, there is the actual use of the application, but when we mentioned SPI, usually refers to the standard SPI, refer to this form of four lines.
Host SPI communication is also our microcontroller, during read and write data timing, there are four modes, four modes to understand this, we first have to learn about two nouns.
CPOL: Clock Polarity, it is the clock polarity.
The clock polarity is what concept? The whole process is divided into an idle communication time and communication time, SCLK and before an idle state after sending the data is high so CPOL = 1, if the idle state SCLK is low, then the CPOL = 0.
CPHA: Clock Phase, it is the phase of the clock.
And exchanging confidential data from the host, it involves a problem that the MOSI output data to the host sampling the data and at what time the slave at any time, or at what time the slave output data to the host what time sampling and MISO this data. Characteristics of a synchronous communication is that all changes and sample data is carried along with the clock edge, that is to say a change in sampling data is always close to the edge or clock. And a clock cycle must contain a rising edge and a falling edge, which is the definition of the determined period, but this is not successively along two predetermined. And because the data generated from the time of its stability is to take some time, then, if the host data output at the rising edge to the MOSI, the machine can only go from this sampling data in the falling edge. Whereas if one of the falling edge of the output data, the other party must be sampled at the rising edge.
CPHA = 1, means that the output data on the first edge of a clock cycle , as this edge is rising or falling, that if the value in CPOL depending, CPOL = 1 that is falling, the contrary is rising along. So naturally it is in the sampled data along the second.
CPHA = 0, it means that the data is sampled on the first edge of a clock cycle, the same in what it is determined by the CPOL. Naturally the output data in a second direction on.
Think for a moment, there will be a question: When is the beginning of a data transmission of the first bit, on the first clock edge to sample the data, then it is when the output come from? There are two cases: one is that the edge energy SSEL, the last two on a clock edge data, may also take effect in both cases simultaneously.
We CPOL = 1 / CPHA = 1, for example, the timing out for everyone to look at the picture, as shown in Figure 1.
We Figure 15-1, and when data is not transmitted after the transmission is completed, SCK are high, so CPOL = 1. As can be seen, in a first direction when the SCK, MOSI and MISO vary, while the second direction when the SCK, the data is stable, the sampled data is appropriate at the moment, i.e. a rising edge of a clock cycle i.e. the trailing edge of the latched read data, i.e. CPHA = 1. Note that the last chip select SSEL most hidden, under normal circumstances, the pin is usually used to determine which master and slave can communicate. The remaining three models, I put the picture out, simplicity and the MOSI MISO together, we look carefully control the look, all the processes are clear theory, help your deep understanding of SPI communication, such as 2 shown in FIG.
Verilog programming
Programming of the communication protocol used on the Figure 1, i.e. (CPOL = 1 / CPHA = 1)
Programming steps:
Receiving module:
1) and the data terminal MCU FPGA end synchronization process.
SPI data output from the MCU, the MCU FPGA not in the same clock domain, may be the most simple D flip-flops to achieve synchronization data. And the rising edge detection consumes two D flip-flops, in order to ensure synchronous SPI data, but also through the two other flip-flop output signal synchronization.
SPI_DATA access edge detection signal and the signal SPI_CS and SPI _SCK: SPI_SCK rising edge of the output data flag; SPI_CS rising edge of the write completion flag data.
2) Design of SPI protocol (data reception).
Determining whether a valid SPI_CS, 8-bit data is captured based on the received enable signal (MCU timing of the rising edge of the sampling signal), captured data string achieved by counter rotation.
3) After completion of the capture of the output enable signal.
The rear end to facilitate response, capturing completion signal output flag.
Transmitting module:
1) and the data terminal MCU FPGA end synchronization process.
SPI_CS just edge detection signal and SPI _SCK: SPI_SCK falling edge of the write data flag; SPI_CS rising edge of the write completion flag data.
2) Design of SPI protocol (data reception).
State machine transmission protocol design, design of the two states, state 1 is the IDLE state waiting for data output is always 0, SEND state to state 2, parallel and serial data is clocked out.
3) completion of the transmission data of the output enable signal.
The rear end to facilitate response, output completion flag signal. Signal is determined by the rising edge of CS.
Transfer: https://blog.csdn.net/gogomusic/article/details/54783969
