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SPI background knowledge
SPI (Serial Peripheral interface) is a serial peripheral interface, which is a high-speed, full-duplex, synchronous communication bus. It was first defined by Motorola on its MC68HCXX series processors.
SPI characteristics
1. Full-duplex serial communication;
2. High-speed data transmission rate;
3. Data transmission is not limited to 8 bits, it can be a word of any size;
4. Very simple hardware structure. A slave does not need a unique address (unlike I2C). The slave uses the master clock and does not require a precision clock oscillator/crystal (unlike UART). No transceiver required (unlike CAN).
Physical layer of SPI bus
SPI is a synchronous data bus, which means that it uses a separate data line and a separate clock signal to ensure perfect synchronization between the sender and receiver.
The clock is an oscillating signal, and the receiving end samples the signal on the data line at the exact timing.
When the master sends to the slave , the master generates a corresponding clock signal, and then the data is sent to the slave from the MOSI signal line one by one; the
master receives the slave data , if the slave needs to send the data back to the master, then The master will continue to generate a predetermined number of clock signals, and the slave will send data through the MISO signal line;
SCLK: clock signal, generated by the Master, for synchronization
MOSI: master data output, slave data input
MISO: master input, slave Data output
SS: Slave device selection line, active low
Note: The master can only communicate with one slave device at a time, otherwise the data will be confused
Start signal: SS changes from high to low, which is the start signal of SPI communication. End
signal: SS changes from low to high, which is the end signal of SPI communication.
The SPI bus is in master-slave mode. The start signal is sent by the host. The slave of the communication, the end signal is also sent by the master to end this communication
SPI standard protocol
SPI has 4 modes, controlled by CPOL (clock polarity) and CPHA (clock phase)
CPOL -> 0: low level when SCLK is idle 1: high level when SCLK is idle
CPHA -> 0: Odd edge data acquisition 1: Even edge data acquisition
CPOL determines whether the transition edge is a rising edge or a falling edge. CPHA only decides which transition edge is sampled.
The combination of the above generates four data transmission modes:
Mode 0: CPOL =0, CPHA =0
Mode 1: CPOL =0, CPHA =1
Mode 2: CPOL =1, CPHA =0
Mode 3: CPOL =1, CPHA =
1Note : To ensure that the communication is normal, the communication modes of the master and the slave need to match
The master and the slave are configured in the same mode, and they can communicate normally:
mode 0 or 3: the master sends data on the falling edge, and the slave collects data on the rising edge
Mode 0 or 3: the slave sends data on the falling edge, and the master collects data on the rising edge
Mode 1 or 2: The rising edge of the host sends data, and the falling edge of the slave collects data
Mode 1 or 2: The rising edge of the slave sends data, and the master collects data at the falling edge
If the timing is inconsistent, it will cause communication failure:
the master works in mode 0 (collecting data on the rising edge, sending data on the falling edge), and the slave (collecting data on the falling edge, sending on the rising edge). At the falling edge, the master sends data, and the slave collects data immediately. At this time, the data is unstable and the communication fails; when the rising edge, the slave sends data, the master sends data, the master collects data immediately, the data is also unstable, and the communication fails.