Source - Author @ Tao Shao &: https://www.cnblogs.com/deng-tao/p/6004280.html
Readers are advised to read the original text to ensure complete information
1. What is SPI
①Serial Peripheral Interface (Serial Peripheral Interface) abbreviation.
② A is a high-speed, full-duplex, synchronous communication bus.
2. Advantages and disadvantages of SPI
Advantages Disadvantages:
①Support full-duplex communication ①No specified flow control
② Simple communication ② There is no response mechanism to confirm whether data is received
③Data transfer rate block3. SPI features
① High-speed, synchronous, full-duplex, non-differential, bus type
② Master-slave communication mode
4. Detailed explanation of protocol communication timing
①The communication principle of SPI is very simple. It works in a master-slave mode. This mode usually has one master device and one or more slave devices, and requires at least 4 wires. In fact, 3 wires can also be used (single when transferring). It is also common to all SPI-based devices, they are SDI (data input), SDO (data output), SCLK (clock), CS (chip select) .
1) SDO/MOSI – master data output, slave data input;
2) SDI/MISO – master data input, slave data output;
3) SCLK – clock signal, generated by the master;
4) CS/SS - Slave device enable signal, controlled by the master device.
When there are multiple slave devices, because each slave device has a chip select pin connected to the master device, when our master device communicates with a slave device, it will need to correspond to the slave device . The chip select pin level is pulled low or pulled high.
②It should be noted that our SPI communication has 4 different modes . Different slave devices may be configured in a certain mode at the factory, which cannot be changed; but our communication parties must work in the same mode. So we can configure the SPI mode of our master device and control the communication mode of our master device through CPOL (clock polarity) and CPHA (clock phase), as follows:
Mode0: CPOL=0, CPHA=0
Mode1: CPOL=0, CPHA=1
Mode2: CPOL=1, CPHA=0
Mode3: CPOL=1, CPHA=1
The clock polarity CPOL is used to configure which state the SCLK level is in an idle state or an active state.
The clock phase CPHA is used to configure which edge the data sample is on.
CPOL=0, it means that it is in an idle state when SCLK=0, so the effective state is that when SCLK is at a high level,CPOL=1, which means that it is in an idle state when SCLK=1, so the effective state is that when SCLK is at a low level,
CPHA=0, Indicates that data sampling is on the first edge, and data is sent on the second edge.
CPHA=1, indicating that data sampling is on the second edge, and data is sent on the first edge.
E.g:
CPOL=0, CPHA=0: When the idle state is at this time, SCLK is at a low level, and the data sampling is on the first edge, that is, the transition of SCLK from a low level to a high level, so the data sampling is rising edge, data transmission is on the falling edge.
CPOL=0，CPHA=1：此时空闲态时，SCLK处于低电平，数据发送是在第1个边沿，也就是SCLK由低电平到高电平的跳变，所以数据采样是在下降沿，数据发送是在上升沿。
CPOL=1，CPHA=0：此时空闲态时，SCLK处于高电平，数据采集是在第1个边沿，也就是SCLK由高电平到低电平的跳变，所以数据采集是在下降沿，数据发送是在上升沿。
CPOL=1，CPHA=1：此时空闲态时，SCLK处于高电平，数据发送是在第1个边沿，也就是SCLK由高电平到低电平的跳变，所以数据采集是在上升沿，数据发送是在下降沿。
需要注意的是：我们的主设备能够控制时钟，因为我们的SPI通信并不像UART或者IIC通信那样有专门的通信周期，有专门的通信起始信号，有专门的通信结束信号；所以我们的SPI协议能够通过控制时钟信号线，当没有数据交流的时候我们的时钟线要么是保持高电平要么是保持低电平。
6、内部工作机制
SSPSR 是 SPI 设备内部的移位寄存器(Shift Register). 它的主要作用是根据 SPI时钟信号状态, 往 SSPBUF 里移入或者移出数据, 每次移动的数据大小由 Bus-Width 以及 Channel-Width 所决定.