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1. Introduction
This article mainly introduces the SPI bus. The second chapter explains the SPI protocol. First, we understand the SPI communication protocol from the hardware, and then explain the four working timing modes of SPI. Chapter 3 introduces STM32's SPI peripherals.
Reference link: link
Two, SPI protocol
1.1 Hardware structure
The SPI protocol uses four wires to communicate: MOSI, MISO, SCK, CS. One SPI master device can connect multiple SPI slave devices. The slave devices share the three wires MOSI, MISO and SCK. Each slave device has its own chip selection CS. (Generally active at low level), the master device provides the working clock SCK.
Picture quoted from: https://www.rt-thread.org/document/site/programming-manual/device/spi/spi/
1.2 Working timing mode The working timing mode of
SPI is determined by CPOL (clock polarity) clock polarity and CPHA (clock phase) clock phase.
- When CPOL=0, the idle level is low (that is, the level before starting communication); when CPOL=1, the idle level is high.
- When CPHA=0, sample at the first SCK transition edge and change the data at the second transition edge; when CPHA=1, sample at the second SCK transition edge.
Understanding: From the perspective of permutation and combination of probability theory, CPOL is condition A, CPHA is condition B, and A and B are independent events. There are four combinations. Signal diagrams can be drawn based on conditions A and B. Take the example of drawing the signal diagram of mode 3 (CPOL=1, CPHA=0), CPOL=1, so the idle level is high, then the first transition edge is the falling edge, CPHA=0, which means from the first Each edge is sampled (that is, the falling edge of the previous analysis), and the data is changed on the rising edge (the crossed part of the signal diagram indicates that the data changes, and the part of the data sampled is unchanged).
Three, STM32 SPI peripherals
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