About the SPI protocol

4-wire
SCLK, clock signal, clock frequency is the SPI rate, and SPI mode related
MOSI, master output, slave input, master data
MISO, master input, slave output
CS, slave device selection, active low
3-wire There
are only 3 lines: SCLK, MOSI and CS, no MISO data line, suitable for simplex communication, the master only sends or receives data from the slave.
There are only 3 wires: SCLK, SDIO and CS. SDIO here is used as a bidirectional port, which is suitable for half-duplex communication. For example, many ADC chips of ADI support bidirectional transmission. When using an FPGA to operate a bidirectional port, it should be set to a high-impedance state z as an input.
4 working modes
CPOL=0 means that SCK is 0 in the idle state
CPOL=1 means that SCK is 1 in the idle state
CPHA=0 means that the input and output data are valid at the first edge of SCK
CPHA=1 means that in The input and output data are valid at the second edge of SCK