A Modelsim+matlab FPGA Image Processing Simulation Method

1. Basic structure

       Use modelsim tool, call Verilog system function, read the image data into the memory group of testbench. After processing, call the system function to save the data into a file. These system functions cannot be integrated into hardware and are only used for simulation testing. The image data needs to be generated by matlab, because ordinary pictures are compressed and stored, and the pictures need to be restored to the original rgb or ycrcb data stream. In the same way, the original data of the saved picture needs to be processed by matlab and converted into a picture format that can be used for display.

2. Calling related system functions

1、$readmemh

Calling method: $readmemh("<data file name>",<memory name>); For example:

`timescale 10ns/1ns
module test;
reg set;
reg[15:0] memory[0:7];    //注意这里每个存储单元的长度为16位，因为每个数字是四位十六进制数，换算成二进制数是16位
reg[4:0] n;
initial
	begin
		$readmemh("file2.txt",memory);
	for(n=0;n<=7;n=n+1)
		$display("%h",memory[n]);
	end
endmodule
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原文链接：https://blog.csdn.net/m0_38037810/article/details/79598647

expand:

(1) $readmemh reads the file in hex format, similarly, $readmemb reads the file in binary format

(2) The file "file2.txt" can include a path. If the path is not included, it will be stored in the same testbench file directory by default. When including the path, use "/",

       如"D:/xxx/file2.txt"

2、$fopen 、$fdisplay

       Writing a file is relatively troublesome. You need to define a variable and use the $fopen statement to open a file to obtain the file handle, and then use the $fdisplay command to write. Of course, there are other file write commands, but every time $fdisplay is written It will automatically switch to the next line, which is more convenient to use

integer out_frame0;
initial
begin//获取文件句柄
    out_frame0 =  $fopen("C:/Users/...../out_frame0.dat","w");
end

always @(posedge pclk)
begin
    if (file_out_en == 1)
        $fdisplay(out_frame0,"%h",pixel_data_wr);
end