FPGA study notes (thirteen) modelsim automated simulation environment

Building an automated simulation based on Modelsim

We usually operate the Modelsim interface before, which is time-consuming and troublesome. Here we introduce a quick method to quickly build a simulation environment through the do file to achieve a more efficient simulation process.

We only need to write the code in sim.do, and then click the modelsim_run.bat file to complete all the simulation process.

Batch file modelsim_run.bat

Just double-click the batch file modelsim_run.bat, Modelsim can be automatically invoked, and the compilation and simulation of the Testbench and the design files to be verified can be automatically completed, and the signals to be observed can be automatically added to the wave window. Fully automated! !

The batch file contains one command:

modelsim -do sim.do

This is a DOS command, which means to call the Modelsim tool and execute the sim.do file in the Modelsim tool.

do file

The sim.do file is written in the tcl scripting language

##create work library
vlib work
vlog    "../src/*.v"
vsim    -voptargs=+acc work.moudle_TB
# Set the window types
view wave
view structure
view signals
add wave -divider {moudle_TB}
add wave moudle_TB/*
.main clear
run 320us

vlib work: Create a work library, which is equivalent to the work library generated when a new project is created. Later, the result information of our compilation is stored in the work library.

vlog "../src/*.v": vlog is equivalent to compile in the modelsim tool, "../src/*.v" means to compile all verilog files in the /src path.

vsim -voptargs=+acc work moudle_TB: vsim means to start the simulation function, and the simulation file is moudle_TB.

add wave -divider {moudle_TB} : Separate all signal lines of
moudle_TB add wave moudle_TB/* : Add the left and right signal lines in the top-level file moudle_TB to the simulation waveform window

.main clear : clears the Transcript window

run 320us: run time 320us