Verilog counter count.v and test bench file, synchronous setting, synchronous clearing, counting function, simulation waveform and analysis

1. Write module count.v and test file tcount.v code:

module count(out,data,load,reset,clk);
output[7:0] out;
input[7:0] data;
input load,clk,reset;
reg[7:0] out;
always @(posedge clk)
  begin
      if(!reset)  out=8'h00;
      else if(load) out=data;
      else              out=out+1;
   end
endmodule



//测试文件tcount.v
`timescale 1ns/1ns
module tcount;
wire[7:0] out;
reg[7:0] data;
reg load,clk,reset;

initial
  begin
     clk = 0;
     #10 forever #10 clk = !clk;
  end

initial 
  begin
      reset=1; load=1; data = 8'h01;
      #40 data = 8'h4;
      #40  data = 8'h20;
      #40  data = 8'h80;
      #40 load=0; 
      #160 reset=0;
   end

//exemplify
count v1_count(
  .out (out),
  .data (data),
  .load (load),
  .reset (reset),
  .clk (clk)
                           );
endmodule

Code analysis:
start to set rst to 1, load to 1, clk starts to have a rising edge at 10s, the first 160ns is a synchronous number setting function, and the output value of out is the data of data. When the load is 0 at the 160ns moment, the counting function is started, and 1 is added to the original value. Reset is set to 0 at the 320ns moment, and the reset operation is performed, so the output is 0.
2. Analysis of simulation results:

3. Analysis of results:
from top to bottom in the simulation waveform are clk, reset, load, data and out. When reset is 1 and load is 1, it is a counting function, and the output value of out is the value of data. When reset is 1 and load is 0, it is a counting function. Every time there is a rising edge, the count value is increased by 1. When reset is 0, the output out is 0, the simulation result is exactly the same as the expected realization, and the experiment is correct.