Brief introduction
Quartus II design is the most advanced and complex, for system-on-a-programmable-chip (SOPC) design environment. Quartus II design to provide better timing closure and block-based design flow LogicLock ™. Quartus II design only comprises a programmable logic device (PLD) and timing closure to block-based design flow as the basic characteristics of the software. Quartus II design software to improve performance and enhance functionality to solve potential design delay, the first to provide a unified workflow FPGA and mask-programmed devices developed in the industrial field.
New Project
1. Create a new folder with the name you are going to build the project name, remember names must be the same name in English
2. Open quartus, click on File-> New Project Wizard
Click next-> select just built a folder location to save the project, the name of the project to be consistent with the file name -> Click next
If you have to add the file to add -> select the components of the model parameters -> next-> confirmation engineering information, Finish
3. Click File-> New-> VHDL File-> OK
VHDL statements written, the picture shows the structure of a multiplexer 4-1 is described below
Compile on Save
An error occurred
lcdf_vhdl library contains func_prims package that VHDL language describes the basic logic gates, latches and flip-flops, we call all the contents of the package by all
There are three ways to add this package
(1) add when creating a project
(2) pre-compiled add
Left-click on Files-> add / remove file in project-> File-> Add to
(3) assighments-> settings-> File-> Add to
Plotting FIG.
点击File->New->Vector Waveform File
Left-click in the blank
点击Insert->Insert Node or Bus->Node Finder
选择Pin:all->list->">>"->OK->OK
Edit->End Time设置截止时间
设置节点波形
（中间应该还有几步）
保存
功能仿真
Processing->Simulate Tool
Simulation mode设置成Functional，点击Generate Functional Simulate Netlist->Start开始仿真
生成电路图
Tools->Nerlist Viewers->RTL Viewer
当当当当，睡觉
