Verilog modules written in simple digital circuits, must be accompanied by a testbench file as a simulation. Of course a simple module can be used to write a simple Verilog testbench simulation simple, but once the function is more complex experience, flexibility Verilog language is certainly less than C / C ++ such language. As a programming language SystemVerilog for verification of object-oriented, to better describe the timing, but also has the flexibility of object-oriented language and reusability, can bring a lot of convenience for engineering simulation. Next, using a simple sequence SystemVerilog detection module for simulation.
First, the project framework
The project a test module detecting a state machine sequence "1110010", contains five files, described as follows:
├── top.sv: top module for connecting each of the following modules
│
│ ├── module_bfm.sv: Bus Functional Model module interface is described for connecting
│
│ ├── tester.sv: generating timing simulation signal
│
│ ├── coverage.sv: the detection module coverage
│
│ ├── module.v: a simulation module to be
Since the module is written in Verilog, Interface is not used directly, but need to be connected in Verilog specification, while the rest of the SV module directly connected BFM.
module top();
seq_fsm_bfm bfm();
coverage converage_i(bfm);
tester tester_i(bfm);
seq_fsm seq_fsm_i(
.in(bfm.in),
.out(bfm.out),
.state(bfm.state),
.clk(bfm.clk),
.reset(bfm.rst_n)
);
endmoduleTwo, SystemVerilog's interface to use
Using Verilog module is connected to the port, regardless of the order of use or the use of the name are connected extremely tedious and error-prone. SystemVerilog interface is somewhat similar to the C / C ++ classes, the entire package module port signal, so that in between the shared module is very easy, which defines a port for connection to a detection module in sequence. While also providing initial and Task interface, to facilitate generating a clock signal and a simple description, herein described interactive clock, a reset signal and a data signal.
//Bus Functional Model
interface seq_fsm_bfm();
logic clk;
logic in;
logic out;
logic[0:2] state;
logic rst_n;
initial begin
clk=0;
forever #10 clk = ~clk;
end
task reset();
rst_n = 0;
@(posedge clk);
@(posedge clk);
rst_n = 1;
endtask
task send_data(bit in_data);
@(posedge clk) in = in_data;
endtask
endinterface //seq_fsm_interfaceThird, functional coverage
Functional coverage for the actual signal sampling define coverpoint, further test signal contains all the recoverable state. We only a simple example of a functional coverage, the step can be simply divided into: 1, the definition of coverage; 2, sampling
module coverage(seq_fsm_bfm bfm);
logic in;
logic out;
logic[2:0] state;
covergroup cg_cov;
coverpoint in;
coverpoint out;
coverpoint state;
endgroup
cg_cov oc;
initial begin
oc = new();
forever begin
@(posedge bfm.clk);
in = bfm.in;
out = bfm.out;
state = bfm.state;
oc.sample();
end
end
endmodulecoverpoint default include all state, i.e., state 3 or more bits comprises 8 states, "000", "001", "010" ......, for some more of state, use negative or list. Using the resulting coverage report as follows:
# COVERGROUP COVERAGE:
# ----------------------------------------------------------------------------------------------------
# Covergroup Metric Goal/ Status
# At Least
# ----------------------------------------------------------------------------------------------------
# TYPE /top/converage_i/cg_cov 100.0% 100 Covered
# Coverpoint cg_cov::in 100.0% 100 Covered
# Coverpoint cg_cov::out 100.0% 100 Covered
# Coverpoint cg_cov::state 100.0% 100 Covered
# Covergroup instance \/top/converage_i/oc 100.0% 100 Covered
# Coverpoint in 100.0% 100 Covered
# covered/total bins: 2 2
# missing/total bins: 0 2
# bin auto['b0] 498 1 Covered
# bin auto['b1] 502 1 Covered
# Coverpoint out 100.0% 100 Covered
# covered/total bins: 2 2
# missing/total bins: 0 2
# bin auto['b0] 994 1 Covered
# bin auto['b1] 4 1 Covered
# Coverpoint state 100.0% 100 Covered
# covered/total bins: 8 8
# missing/total bins: 0 8
# bin auto['b000] 394 1 Covered
# bin auto['b001] 222 1 Covered
# bin auto['b010] 127 1 Covered
# bin auto['b011] 142 1 Covered
# bin auto['b100] 64 1 Covered
# bin auto['b101] 31 1 Covered
# bin auto['b110] 14 1 Covered
# bin auto['b111] 4 1 Covered Fourth, the tester Tester
Here the tester is relatively simple, but at the reset BFM 01 and generating a random signal.
module tester(seq_fsm_bfm bfm);
initial begin
bit in_data;
bfm.reset();
repeat(1000) begin
// $display("@%0t\n",$time);
in_data = ($random) %2;
bfm.send_data(in_data);
end
$stop;
end
endmoduleFive, Modelsim simulation automation
Modelsim simulation steps can be roughly divided into the compilation and simulation, simulation each time the compiler, add waveform simulation is very cumbersome. You can write scripts to automate do simulation, do the following documents:
if [file exists "work"] {vdel -all}
vlib work
vlog top.sv tester.sv seq_fsm_bfm.sv coverage.sv seq_fsm.v #编译文件，注意路径，这里与do文件同目录
vopt top -o top_optimized +acc +cover=sbfec+seq_fsm(rtl). #指定顶层文件，优化
vsim top_optimized -coverage #开始仿真
set NoQuitOnFinish 1
onbreak {resume}
log /* -r
add wave seq_fsm_i/* #添加波形
run -all
vcover report seq_fsm.ucdb -cvg -details #报告覆盖率Write good run.do file, run directly under Linux
vsim -do run.do
Reference:
Chris Spear, preparation of guidelines SystemVerilog verification testbench
Ray Salemi, The UVM Primer