Table of contents
3. Schematic diagram of displacement
2. Hardware circuit & pin definition
4. Precautions for Flash operation
4. Software SPI read and write W25Q64
5. SPI communication peripherals
Preface
Statement: The study notes are from Jiangsu University of Science and Technology’s Automated Chemistry Association Station B tutorials and are for learning and communication only! !
The learning of SPI communication is the same as that of I2C, which is divided into software simulation implementation and hardware configuration implementation to read and write W25Q64 Flash memory!
SPI transmits data faster, and the protocol does not strictly stipulate the maximum transmission speed, which depends on the needs of chip manufacturers; the design of SPI is relatively simple and rough, and the functions realized are not as many as I2C, which is relatively simple; the hardware overhead of SPI is relatively large, and the number of communication lines There are many, and there is often a waste of resources in the communication process - " Children from rich families, rich and willful ", only care about completing tasks quickly!
1. SPI communication protocol
1 Overview
①SPI (Serial Peripheral Interface) is a universal data bus developed by Motorola.
②Four communication lines : SCK (Serial Clock), MOSI (Master Output Slave Input), MISO (Master Input Slave Output), SS (Slave Select). Synchronous , full duplex
③Supports mounting multiple devices (one master, multiple slaves). There are several SS lines as there are several slaves . It is very convenient to specify the slave, just set the trigger level for the corresponding line. The pins on the slave are often written as DO or DI, which are connected to the MISO and MOSI of the host respectively.
2. Hardware circuit
①The SCK, MOSI, and MISO of all SPI devices are connected together;
②The host also leads out multiple SS control lines, which are connected to the SS pins of each slave. Only one slave can be selected at the same time.
③The output pin is configured as a push-pull output , and the input pin is configured as a floating or pull-up input . The push-pull output has strong driving capabilities for both high and low levels, which will make the falling edge of the SPI pin signal very fast and the rising edge very fast (unlike I2C, where the falling edge is fast and the rising edge is slow), and the signal changes quickly. Higher transmission speeds (MHz level) can be achieved. It’s not that I2C doesn’t want to use this push-pull output, but because I2C needs to achieve half-duplex, often needs to switch input and output, and needs to achieve multi-master clock synchronization and bus arbitration. These functions do not allow I2C to use push-pull output. Otherwise, the power supply will be short-circuited accidentally. If he chooses more functions, he will naturally give up stronger performance. SPI also has a conflict point , such as the MISO pin in the picture. One input of the master is connected to three outputs of the slave. If the three slaves are always push-pull output, it will inevitably cause a conflict, so there is a provision in the SPI protocol : When the slave's SS pin is high (not selected), the slave's MISO pin must be switched to a high-impedance state (equivalent to the pin being disconnected and not outputting any level). When the slave's SS When it is low level, the MISO pin is allowed to be a push-pull output.
3. Schematic diagram of displacement
The shift diagram is the core of SPI hardware circuit design
The shift registers of both the master and the slave have a clock input (SCK arrow). SPI is generally high-bit first, so every clock shift register will shift to the left. The same is true for the master and the slave. The clock source of the shift register is provided by the host, which is called the baud rate generator here. The clock it generates drives the shift register of the host to shift, and is also output to the shift register of the slave through the SCK pin.
Circuit workflow : First, specify the rising edge of the clock, all shift registers move one bit to the left, and the shifted bit is placed on the pin (the communication line is actually the output data register); on the falling edge of the clock, the pin The bit samples are input to the lowest bit of the shift register . Assume that the host has data 10101010 to be sent to the slave, and at the same time the slave has data 01010101 to be sent to the host... "turning in circles" as shown in the figure will be realized after eight clocks. SPI transceiver is based on byte exchange . When the host needs to send a byte and receive a byte at the same time, it can execute the byte exchange timing. What if you only want to send but don't want to receive? The timing of exchanging bytes is still used, and sending and receiving are performed at the same time. It is just that the received data (usually 0x00 or 0xFF is sent uniformly ) is not read.
Two, SPI timing
1. Timing basic unit
① Starting condition : SS switches from high level to low level. SS is the slave selection line, which is active at low level. Once the slave is selected, communication starts.
②Termination condition : SS switches from low level to high level.
③Exchange one byte
(Mode 0)
CPOL=0: In idle state, SCK is low level
CPHA=0: The first edge of SCK shifts in data (odd edges perform data sampling), and the second edge shifts out data. However, the data must be moved out first and then moved in, so before the first edge of SCK, the data must be moved out in advance. As shown in the figure, it is almost synchronized with the SS falling edge start signal and before the first rising edge of SCK. Press mode 0 during our actual operation!
(Mode 1)
CPOL=0: In idle state, SCK is low level
CPHA=0: The first edge of SCK shifts data out, and the second edge shifts data in (even-numbered edges perform data sampling). It is more common sense to move data out first and then move data in. In practical applications, mode 1 and mode 0 are most commonly used!
(Mode 2)
CPOL=1: In idle state, SCK is high level
CPHA=0: The first edge of SCK shifts in data (odd edges perform data sampling), and the second edge shifts out data.
(mode 3)
CPOL=1: In idle state, SCK is high level
CPHA=0: The first edge of SCK shifts data out, and the second edge shifts data in (even-numbered edges perform data sampling).
Comparison between mode 0 and mode 2 : CPOL is opposite, the idle state level is different, that is, the SCK polarity is reversed; the rest of the process is the same.
Comparison between mode 1 and mode 3 : same as above.
Note : CPHA indicates the clock phase, which determines whether the first clock sample is shifted in or the second clock sample is shifted in, and it does not specify rising edge sampling or falling edge sampling.
2. Complete timing waveform
Of course, each chip has different definitions of the SPI timing byte stream function. Here we take the timing of the practical chip W25Q64 as an example to explain. SPI's regulation of byte stream function is not like that of I2C. The regulation of I2C is generally that the first byte of the effective data stream is the register address, followed by the read and write data, and the read and write register model used;
In SPI, the model of instruction code plus reading and writing data is usually used. The process is that after SPI starts, the first data exchanged and sent to the slave is generally called instruction code, and a corresponding one is defined in the slave. Instruction set, when we need to send any instruction, we can send the data in the instruction set in the first byte after the start, so as to guide the slave to complete the corresponding function, and different instructions can have different numbers of instructions , some instructions can be completed with only one instruction code, such as W25Q64 write enable, write disable and other instructions, while some instructions need to follow the data to be read and written, such as W25Q64 write data, read data Wait, the write data instruction must be followed by where to write and what to write, and the same is true for reading data.
The following pictures may not be clear, please refer to the tutorials of Jiangsu University of Science and Technology for details !
Send command: Specify the device to SS and send command (0x06)
Specified address write: Send a write command (0x02) to the device specified by SS, and then write the specified data (Data) at the specified address (Address[23:0])
Specified address read: Send a read command (0x03) to the device specified by SS, and then read the slave data (Data) at the specified address (Address[23:0])
In addition to the above, there are other timings, but they are similar: start, exchange, exchange, exchange..., stop . You only need to pay attention to the function definition of each byte, and you can easily use SPI to control the device. .
3. W25Q64 memory chip
1. Chip introduction
①The W25Qxx series is a low-cost, miniaturized, easy-to-use non-volatile memory (not lost when powered off) , which is often used in data storage, font storage, firmware program storage and other scenarios. Memory is divided into volatile memory and non-volatile memory. The former includes SRAM, DRAM, etc., and the latter includes E2PROM, Flash, etc.
②Storage medium: Nor Flash . The program memory of STM32, U disk, solid state drive in the computer, etc. are all Flash memory. Flash memory is divided into Nor Flash and Nand Flash.
③Clock frequency: 80MHz , 160MHz (equivalent frequency of Dual SPI dual SPI mode), 320MHz (Quad SPI quadruple). Learn about dual and quadruple SPI, this section is not used ! It means one clock sends or receives 2 bits/4 bits, which is a bit parallel!
④Storage capacity ( 24-bit address ):
- W25Q40: 4Mbit/512KByte (bit divided by 8 to convert to Byte)
- W25Q80： 8Mbit/1MByte
- W25Q16： 16Mbit/2MByte
- W25Q32： 32Mbit/4MByte
- W25Q64： 64Mbit/8MByte
- W25Q128： 128Mbit/16MByte
- W25Q256: 256Mbit/32MByte
2. Hardware circuit & pin definition
"/" means the same as "-", low level is valid!
WP (Write Protect) write protection , active at low level. In conjunction with the internal register configuration, hardware write protection can be achieved, which prevents writing when the level is low.
HOLD data is maintained , low level is active, and is not used much. If an interrupt suddenly occurs during normal reading and writing, and you want to use the SPI communication line to control other devices, if you set CS back to high level, the sequence will be terminated, but you want to operate other devices without terminating the bus. device, which can set the HOLD pin to a low level , so that the chip can be held on HOLD—the chip releases the bus, but the chip timing will not be terminated, it will remember the current state, and when other devices are operated, it can be used again Set HOLD back to high level , and then continue the timing sequence before HOLD.
The IO0~IO3 in parentheses in the pin diagram are related to the dual and quadruple SPI mentioned above, so don’t worry about it here!
C1 in the circuit schematic diagram is the power filter, R1 and D1 are a power indicator light, HOLD and WP are both active low levels connected to VC!
3.Chip block diagram
Flash space division:
Generally, a storage space can be divided into several blocks first, and each block can be divided into several sectors, and each sector can be divided into many pages.
The large rectangular space on the right side of the picture above contains all memories. Memory is measured in bytes, and each byte has a unique address. The address width of W25Q64 is 24 bits (3 bytes), and the maximum addressing range is 16MB . The large rectangular address range is 000000h~7FFFFFh (8MB), and only half of the address space is used. Taking 64KB as a basic unit, it is divided into 128 Blocks. Pay attention to the address pattern xx0000~xxFFFFh in each Block.
The rectangle in the upper left corner is to further divide each block into multiple sectors. As shown in the figure, the dotted lines point to each Block, which means that each block looks like this. A Block is divided into 16 Sectors in units of 4KB, and the address change pattern in each Sector is xxx000~xxxFFFh.
The Sector is continued to be divided into several Pages. The size of a Page is 256 bytes , that is, a Sector can be divided into 16 Pages. The address changes in each Page are xxxx00~xxxxFFh. That is, the address change within the page (Page) is limited to the lowest byte!
Control logic & status register:
The lower left corner is the SPI control logic , that is, the address latching, data reading and writing, etc. inside the chip can be automatically completed by it. Just like the administrator of the entire chip, just tell it what needs to be done, and it will automatically operate the internal circuit to complete the function. ! On the left are the communication pins.
There is a status register (Status Register) on the control . Whether the chip is in a busy state, whether it is write-enabled, and whether it is write-protected can be reflected here!
Page cache area:
The 256-Byte Page Buffer is actually a 256-byte RAM memory,... Data reading and writing are carried out throughthis RAM buffer area . The written data will be placed in the RAM buffer area first, and then the chip will copy the data in the buffer area to the corresponding Flash after the sequence is over for permanent storage! Why is this so? Because the frequency of SPI writing is very high, and the writing speed of Flash is relatively slow because it needs to be powered off without loss (leaving unforgettable changes), while the speed of RAM in the cache area is very fast. However, because the cache area only has 256 bytes, the amount of data written continuously in one writing sequence cannot exceed 256 bytes . Since it takes a certain amount of time for the data to be transferred from the cache area to the Flash memory, the chip will enter a busy state after the write sequence is over. As shown in the figure, there is a line leading to the status register (Status Register), and the BUSY bit is set to 1 . At this time, the chip will not respond to the new read and write timing.
other:
Write Control Logic is connected to the WP pin and cooperates with it to complete hardware write protection. High Voltage Generators (High Voltage Generators) are programmed in conjunction with Flash. In order to keep Flash from being lost when it is powered off, it is necessary to produce "unforgettable" changes in the memory, which generally require high voltage stimulation. Page Address Latch/Counter (Page Address Latch/Counter) and Byte Address Latch/Counter (Byte Address Latch/Counter), these two are used to specify the address : STM32 sends a total of 3 bytes through SPI Address, because 1 Page is 256 bytes, the byte address within a page depends on the lowest byte. The high-order 2 bytes sent (the first 2) correspond to the page address. They will enter the Page Address Latch/Counter, and the last byte will enter the Byte Address Latch/Counter.
Then the page address selects which page we want to operate through write protection and row decoding , and the byte address performs the read and write operations of the specified address through column decoding and 256-byte cache . This address pointer can automatically +1 after reading and writing , so that it is easy to achieve the purpose of continuously reading and writing multiple bytes starting from the specified address.
4. Precautions for Flash operation
In order to maintain the characteristics of Flash not being lost after power failure, large storage capacity, and low enough cost, it will make some compromises and concessions in terms of operation convenience, so there are many precautions. RAM is different. You can write wherever you want, as much as you want, and it can be overwritten. Subsequent data can directly overwrite the original data.
①During writing operation:
- Write enable must be performed before writing operation
- Each data bit can only be rewritten from 1 to 0, but cannot be rewritten from 0 to 1.
- It must be erased before writing data. After erasing, all data bits become 1. After issuing the erase command, the chip will also enter the busy state.
- Erase must be performed by the smallest erase unit . You can choose whole chip erase, block erase, sector erase, it doesn’t get any smaller.
- When multiple bytes are written continuously, a maximum of one page of data is written , and data beyond the end of the page will be returned to the top of the page and overwritten. When performing multi-byte writing, the address range cannot span the edge of the page , otherwise the address will be confused.
- After the write operation is completed, the chip will enter the busy state and will not respond to new read and write operations.
②During reading operation:
- Directly call the read sequence, no need to enable (1), no additional operations (234), no page limit (5), it will not enter the busy state after the read operation is completed, but it cannot be read in the busy state.
Continue to the next article (practical operation):
4. Software SPI read and write W25Q64
5. SPI communication peripherals
6. Hardware SPI read and write W25Q64
Highlights from past issues:
STM32 timer input capture (IC)
STM32 timer output comparison (PWM wave)
STM32 timed interrupt
STM32 external interrupt
STM32GPIO detailed talk
...