2.3.5 Ethernet Interface
The Ethernet interface consists of MAC ( Ethernet Media Access Controller ) and PHY ( Physical Interface Transceiver ). The Ethernet MAC is defined by the IEEE802.3 Ethernet standard and implements the data link layer. Commonly used MAC supports two rates of 10Mbit/s or 100Mbit/s. Gigabit Ethernet is the next-generation technology of Fast Ethernet, increasing the speed to 1000Mbit/s. Gigabit Ethernet was released as IEEE 802.3z and 802.3ab as a complement to the IEEE 802.3 standard.
The MII (Media Independent Interface) connection is used between the MAC and the PHY, which is an Ethernet industry standard defined by IEEE-802.3, including a data interface and a management interface between the MAC and the PHY. The data interface includes two independent channels for sending and receiving respectively. Each channel has its own data, clock and control signals. The MII data interface requires a total of 16 signals. The MII management interface contains two signals, one is a clock signal and the other is a data signal. Through the management interface, upper layers can monitor and control the PHY. The hardware circuit principle of an Ethernet interface is shown in Figure 2.15.
Figure 2.15 The hardware circuit principle of the Ethernet interface
From the CPU to the final interface are CPU, MAC, PHY, Ethernet isolation transformer, and RJ45 socket. The Ethernet isolation transformer is a magnetic component between the Ethernet transceiver chip and the connector, which plays the role of signal transmission, impedance matching, waveform repair, signal clutter suppression and high-voltage isolation between the two .
Many processors integrate MAC (media access controller) or both MAC and PHY (physical interface transceiver), and many Ethernet control chips also integrate MAC and PHY.