For applications in many specific occasions, some specific types of RAM (random access memory) are often used in embedded systems.
1. DPRAM: Dual Port RAM
The characteristic of DPRAM is that it can be accessed through two ports at the same time. It has two sets of completely independent data bus, address bus and read and write control lines. It is usually used to exchange data between two processors, as shown in Figure 2.6. When one end is written with data, the other end can know by polling or interrupt, and read the data written by it. Since the arbitration logic circuit when dual CPUs (Central Processing Units) access the DPRAM at the same time is integrated in the DPRAM, the circuit principle designed by the hardware engineer is relatively simple.
Figure 2.6 Dual-port RAM
The advantages of DPRAM are that the communication speed is fast, the real-time performance is strong, the interface is simple, and both processors can actively carry out data transmission. In addition to dual-port RAM, chip manufacturers such as IDT have also introduced multi-port RAM, which can allow more than three processors to exchange data.
2.CAM: Content Addressable RAM
CAM is a content-addressable memory. It is a special storage array RAM. Its main working mechanism is to automatically compare an input data item with all the data items stored in the CAM at the same time. Whether the data items stored in the CAM match, and output the matching information corresponding to the data items.
As shown in Figure 2.7, in CAM, the input is the data to be queried, and the output is the data address and matching flag. If there is a match (that is, data is found), the data address is output. The advantage of CAM for data retrieval is unmatched by software, and it can greatly improve system performance.
Figure 2.7 Input and output of CAM
3.FIFO: first in first out queue
FIFO memory is characterized by first-in, first-out, orderly in and out, and FIFO is mostly used for data buffering. FIFO is similar to DPRAM and has two access ports, but the ports on both sides of the FIFO are not equal, and can only be set to one side as input and one side as output at a certain time.
If the area of the FIFO has a total of n bytes, the area can only be read out by reading the same address for n times, and the offset address cannot be specified. For a FIFO with n pieces of data, after reading m times cyclically, the m+1th data will be automatically read in the next read, which is determined by the characteristics of the FIFO itself.
Summarizing the content of Section 2.2, the memory classification shown in Figure 2.8 can be obtained.
Figure 2.8 Memory Classification