2.2 Memory
Memory can be mainly divided into read-only memory (ROM), flash memory (Flash), random access memory (RAM), optical/magnetic media memory.
ROM can be further subdivided into non-programmable ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and electrically erasable programmable ROM (E2PROM). convenient.
NOR (NOR) and NAND (NAND) are the two main Flash technologies on the market. Intel first developed NOR Flash technology in 1988, which completely changed the situation that EPROM and EEPROM dominated the world. In 1989, Toshiba released the NAND Flash structure, and the cost per bit was greatly reduced.
The interface between NOR Flash and CPU is a typical SRAM-like interface (as shown in Figure 2.5), and no additional control circuit is required. The characteristic of NOR Flash is that it can be executed in the chip, and the program can run directly in the NOR. The interface between the NAND Flash and the CPU must be converted by the corresponding control circuit, and the signal of the NAND Flash interface can also be generated through the address line or GPIO. NAND Flash is accessed in block mode and does not support in-chip execution.
Figure 2.5 Typical SRAM-like interface
The Common Flash Interface (CFI) is an open, standard interface for reading data from NOR Flash devices. It enables the system software to query various parameters of the installed Flash device, including device array structure parameters, electrical and time parameters, and functions supported by the device. If the chip does not support CFI, JEDEC (
Joint Electron Device Engineering Council
, Federation of Electronic and Electrical Equipment) should be used. The NOR of the JEDEC specification cannot directly read information such as capacity through commands. It is necessary to read the manufacturer ID and device ID to determine the size of the Flash.
Different from the SRAM-like interface of NOR Flash, a NAND Flash interface mainly includes the following signals:
I/O bus: Addresses, instructions, and data are transmitted through this group of buses, typically
8 or 16 bits
.
Chip Enable (CE): If the CE signal is not detected, the NAND device remains in standby mode and does not respond to any control signal.
Write Enable (WE): WE is responsible for writing data, addresses or instructions into NAND.
Read Enable (RE): RE allows data output.
Command Latch Enable (CLE): When CLE is high, on the rising edge of the WE signal, the command will be latched into the NAND command register.
Address Latch Enable (ALE): When ALE is high, on the rising edge of the WE signal, the address will be latched into the NAND address register.
Ready/Busy (R/B): If the NAND device is busy, the R/B signal will go low. This signal is open-drain and requires a pull-up resistor.
NAND Flash has larger capacity and lower price than NOR Flash; the maximum number of erasing and writing of each block in NAND Flash is 1 million times, while the number of erasing and writing of NOR Flash is 100,000 times; the erasing and programming speed of NAND Flash is much higher than that of NOR Flash. Flash.
Due to the inherent electrical characteristics of Flash, in the process of reading and writing data, one or several data errors may occur occasionally, that is, bit inversion. The probability of bit inversion in NAND Flash is much greater than that in NOR Flash. Bit reversal cannot be avoided, therefore, error detection/error correction (EDC/ECC) algorithms should be used while using NAND Flash.
The programming principle of Flash is that only 1 can be written as 0, but 0 cannot be written as 1.
Therefore, before Flash programming, the corresponding block must be erased, and the erasing process is the process of writing all bits as 1, and all bytes in the block become 0xFF. In addition, there is also a
load
balancing problem in Flash, and erasing and writing cannot always be performed at the same block location, which may easily lead to bad blocks.
Currently, NOR Flash can be accessed using the SPI interface to save pins. Compared with traditional parallel NOR Flash, SPI NOR Flash only needs 6 pins to realize the interface communication of single I/O, dual I/O and 4 I/O ports, and some SPI NOR Flash also supports DDR mode, which can further increase the access speed to 80MB/s.
IDE (Integrated Drive Electronics) interface can be connected to hard disk controller or optical drive, the signal of IDE interface is similar to SRAM. The IDE interface is also commonly referred to as the ATA (Advanced Technology Attachment) interface, but from a technical point of view, this is not accurate. In fact, the ATA interface has developed so far, and has experienced ATA-1 (IDE), ATA-2 (Enhanced IDE/Fast ATA, EIDE), ATA-3 (FastATA-2), Ultra ATA, Ultra ATA/33, Ultra ATA/ 66. The development process of Ultra ATA/100 and Serial ATA (SATA).
Many SoCs integrate an eFuse electrical programming fuse as an OTP (One-Time Programmable, one-time programmable) memory. eFuse can configure the internal parameters and functions of the chip through a computer, which is generally set when the chip leaves the factory.
The various ROM, Flash, and magnetic media memories described above all belong to the category of non-volatile memory (NVM), where information is not lost when power is lost, while RAM is the opposite.
RAM can also be subdivided into static RAM (SRAM) and dynamic RAM (DRAM). DRAM stores in the form of electric charge and data is stored in capacitors. Because capacitors lose charge due to leakage, DRAM devices require periodic refresh. SRAM is static, it will hold a value as long as it is powered, SRAM has no refresh cycle. Each SRAM memory cell consists of 6 transistors, while the DRAM memory cell consists of 1 transistor and 1 capacitor.
Generally speaking, SDRAM and DDR SDRAM belong to the category of DRAM, and they work with a clock synchronized with the CPU external memory controller (note that it is not the same as the operating frequency of the CPU). Compared with SDRAM, DDR SDRAM utilizes the rising edge and falling edge of the clock pulse to transmit data at the same time, so the data transmission frequency is doubled under the condition of the same clock frequency. In addition, there are RDRAM (Rambus DRAM) and Direct RDRAM using RSL (Rambus Signaling Level, Rambus Signaling Level) technology.