2.6 Hardware Timing Analysis
2.6.1 The concept of timing analysis
Driver engineers generally do not need to analyze the timing of hardware, but many in-house driver engineers also need to undertake the task of circuit board debugging. Therefore, it is necessary to master the method of timing analysis.
For drive engineers or hardware engineers, timing analysis is to make the access between chips meet the requirements of the effective sequence, sampling setup time (Setup Time) and hold time (Hold Time) of the timing diagram signals in the chip data sheet. When the board is not working properly, pinpoint timing problems.
The setup time refers to the time that the data has remained stable before the edge of the clock signal of the flip-flop arrives. If the setup time is not enough, the data will not be clocked into the flip-flop on this clock edge; the hold time refers to the clock of the flip-flop. After the signal edge arrives, the data needs a stable time. If the holding time is not enough, the data cannot be entered into the flip-flop.
2.6.2 Typical Hardware Timing
The most typical hardware timing is the read and write timing of SRAM (Static Random Access Memory). The signals involved in the read/write process include address, data, chip select, read/write, byte enable and ready/busy. For a 16-bit, 32-bit (or even 64-bit) SRAM, byte enables indicate which bytes are read and written.
Figure 2.26 shows the read timing of SRAM.
Figure 2.26 SRAM read timing diagram
First, the address to be read (written) is output on the address bus, then the SRAM chip select signal is issued, then the read (write) signal is output, and then the read (write) signal has to go through several waiting cycles. When the SRAM read (write) speed is relatively slow, the waiting period can be set by the corresponding register of the MCU, or it can be reported to the CPU through the device ready/busy (nWait in Figure 2.27), so that the waiting period will be automatically added during the reading and writing process. cycle.
NOR Flash and many peripheral control chips use SRAM-like access timing, so it is important to have a firm grasp of this timing. Generally, in the timing diagram given in the chip data sheet, the meaning and requirements of each period in the figure will be given. The real circuit board must meet the minimum requirements for the setup time and hold time described in the chip data sheet.