Table of contents
Ethernet EMC interface circuit design and PCB design
Typical application of Ethernet in Figure 1 below.
5. Circuit lightning protection design:
7. PCB layout and routing principles:
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Ethernet EMC interface circuit design and PCB design
The network interfaces we use today are all Ethernet interfaces , and most processors currently support Ethernet interfaces. At present, Ethernet mainly includes three interfaces: 10M, 10/100M, and 1000M according to the rate. 10M is rarely used, and it is basically replaced by 10/100M. At present, the Ethernet interface type of our products mainly adopts twisted pair RJ45 interface, which is basically used in the field of industrial control. Due to the particularity of the field of industrial control, we are very particular about the selection of Ethernet components and PCB design. From the perspective of hardware, the Ethernet interface circuit is mainly composed of two parts: MAC (Media Access Controlleroler) control and physical layer interface (Physical Layer, PHY). Most processors include Ethernet MAC control inside, but do not provide a physical layer interface, so a physical chip needs to be connected to provide an Ethernet access channel. Faced with such a complex interface circuit, I believe that all hardware engineers want to know how the hardware circuit is implemented on the PCB.
Typical application of Ethernet in Figure 1 below.
Our PCB design is basically based on this block diagram for layout and wiring. Below we use this block diagram to explain in detail the key points of Ethernet-related layout and wiring.
Figure 1 Typical application of Ethernet
1. Figure 2. The network port transformer is not integrated in the reference circuit PCB layout and wiring diagram of the network port connector.
The following will introduce the layout and wiring points of the Ethernet circuit in Figure 2.
Figure 2 The transformer is not integrated in the circuit PCB layout and wiring reference of the network port connector
a) The distance between the RJ45 and the transformer should be as short as possible, the crystal oscillator should be kept away from the interface, PCB edge and other high-frequency devices, traces or around magnetic components, and the distance between the PHY layer chip and the transformer should be as short as possible, but sometimes for It may be difficult to satisfy the overall layout, but the maximum distance between them is about 10~12cm. The principle of device layout is usually placed according to the signal flow direction, and must not go around;
b) The power supply filter of the PHY layer chip is designed according to the requirements of the chip. Usually, a decoupling capacitor needs to be placed at each power supply terminal. They can provide a low impedance path for the signal and reduce the resonance between the power supply and the ground plane. In order to make the capacitor It plays the role of decoupling and bypass, so it is necessary to ensure that the loop area of the decoupling and bypass capacitors composed of capacitors, traces, vias, and pads is as small as possible, and the inductance of the leads is as small as possible;
c) The filter capacitor from the center tap to ground on the PHY layer chip side of the network port transformer should be as close as possible to the transformer pins to ensure the shortest leads and the smallest distributed inductance;
d) The common-mode resistance and high-voltage capacitor on the interface side of the network port transformer are placed close to the center tap, and the wiring is short and thick (≥15mil);
e) The two sides of the transformer need to cut the ground: that is, the RJ45 connection socket and the secondary coil of the transformer use a separate isolated ground, the isolation area is more than 100mil, and there is no power supply and ground plane under this isolation area. This splitting process is to achieve the isolation of the primary and secondary, and control the interference at the source end to be coupled to the secondary through the reference plane;
f) The power line of the indicator light and the driving signal line are routed adjacent to each other to minimize the loop area. The indicator light and the differential line should be isolated as necessary, and the distance between the two should be sufficient. If there is space, they can be separated by GND;
g) The resistors and capacitors used to connect GND and PGND need to be placed in the ground division area.
2. Ethernet signal lines exist in the form of differential pairs (Rx±, Tx±). Differential lines have strong common-mode suppression capabilities and strong anti-interference capabilities. However, improper wiring will cause serious signal integrity. sexual issues.
Let's introduce the main points of differential line processing one by one:
a) Prioritize drawing Rx± and Tx± differential pairs, try to keep the differential pairs parallel, equal in length, and short in distance, and avoid vias and crossovers. Due to factors such as pin distribution, vias, and routing space, the length of the differential line is likely to be mismatched, the timing will be shifted, and common-mode interference will be introduced to reduce the signal quality. Therefore, correspondingly, compensation should be made for the mismatch of the differential pair to match the line length. The length difference is usually controlled within 5mil. The compensation principle is where the length difference occurs and where to compensate;
b) When the speed requirement is high, it is necessary to control the impedance of the Rx± and Tx± differential pairs, usually the impedance is controlled at 100Ω±10%;
c) The differential signal termination resistor (49.9Ω, some PHY layer chips may not have it) must be placed close to the Rx± and Tx± pins of the PHY layer chip, which can better eliminate the signal reflection in the communication cable. Power supply, some are grounded through capacitors, which is determined by the PHY chip;
d) The filter capacitors on the differential line pair must be placed symmetrically, otherwise the differential mode may be converted into common mode, causing common mode noise, and there must be no stub in the wiring, so as to have a good ability to suppress high-frequency noise.
3. The PCB layout and wiring of the Ethernet circuit where the transformer is integrated in the connector is relatively simpler than that of the unintegrated one.
Figure 3 below is a reference diagram of the PCB layout and wiring of the network port circuit using the integrated connector:
Figure 3 Network port PCB layout and wiring reference diagram of the integrated connector
As can be seen from the above figure, the difference between Figure 3 and Figure 1 is that the network port transformer is missing, and the others are basically the same. The main difference is that the network port transformer has been integrated into the connector, so the ground plane does not need to be divided, but we still need to connect the shell of the integrated connector to the continuous ground plane.
4. Circuit filter design:
a) Connect 10R resistors in series on the differential lines, and add 5-10pF capacitors to the ground respectively
b) Add LC filter to the transformer power supply, choose 600R/100Mhz magnetic beads and 0.01-0.1uF capacitor
5. Circuit lightning protection design:
In order to meet the lightning protection test requirements of IEC61000-4-5 or GB17626.5 standard, common mode 2KV, differential touch 1KV, the lowest-cost design solution is that the primary center tap of the transformer is grounded through the lightning protection device, and a semiconductor discharge with low cost can be selected. tube, but it should be noted that "the nominal voltage of the protective device is required to be greater than or equal to 6V; the peak current requirement of the protective device is greater than or equal to 50A; Current" must be greater than the working voltage and current of the circuit.
According to the test standard requirements, for unshielded balanced signals, differential mode testing is not mandatory, so for the protection requirements of differential mode within 1KV, it can be achieved through the winding of the transformer itself. To protect against energy impact, there is no need to add differential mode protection devices.
1) Since the response of the TVS tube is faster than that of the varistor and the gas discharge tube, the varistor or the gas discharge tube and the TVS tube cannot be directly used in parallel, but a uH-level inductor or wire should be connected in series in the middle (the wire also has parasitic inductance) ;
2) The gas discharge tube needs freewheeling interruption: that is, it must be able to return to the open circuit state after it absorbs the transient short circuit, that is, in general use, the DC breakdown voltage of the gas discharge tube is much higher than the working voltage of the parallel signal , when the gas discharge tube works due to transient interference, after a short circuit occurs, a voltage is required to maintain the short circuit state. If the signal voltage keeps the gas discharge tube in the short circuit state, the signal will be burned over time, so Make the signal voltage lower than the voltage that maintains the gas discharge tube in a short circuit state.
6. Radiation and ESD:
a) Add magnetic beads to the indicator light wiring and power supply, the magnetic beads are close to the interface, and then the current limiting resistor is close to the PHY chip, and capacitor filtering is added.
7. PCB layout and routing principles:
7.1 The transformer is not integrated into the RJ45 interface:
1) Between the transformer and RJ45, the distance between the PHY layer chip and the transformer should be controlled within 1inch
Inside. When the layout conditions are limited, the distance between the transformer and the RJ45 should be kept within 1 inch.
2) The device layout is placed according to the signal flow direction, and do not go around.
3) The ground plane below the transformer should be divided, the width of the dividing line should not be less than 100MIL, and the network port should be transformed
The device is placed on the dividing line between GND and PGND.
4) Each pair of differential traces must control the length of the traces to be the same,
At the same time, note that the control impedance is 50 ohms.
5) Note that the digital ground and analog ground of the PHY layer chip are unified, and the use of digital power and analog power
magnetic beads for isolation. At the same time, it should cooperate with the transformer. Pay attention to the power filter of the PHY chip and design it according to the requirements of the chip.
6) The 3.3V or 2.5V power line of the network port indicator light comes from the power plane, so use them
Magnetic beads and capacitors are used for decoupling; indicator light drive lines should be close to the PHY series resistors, and capacitor filtering should be performed before entering the I/O area. This prevents noise from coupling through the LED power lines into the differential pair area.
7) The indicator light power line and drive signal line should be routed close to each other to minimize the loop area.
8) The indicator line and the differential line pair should be isolated as necessary, and the distance between the two should be far enough, and the GND plane should be used for isolation if necessary.
9) Note that the filter capacitor from the center tap on the chip side of the network port transformer to the ground should be as close as possible to the transformer
pins, to ensure the shortest leads and the smallest distributed inductance.
10) The 0-ohm resistor or capacitor used to connect GND and PGND should be placed on the ground split line.
11) The analog power supply of the PHY chip should not occupy a large area of the plane, from the local copper skin through the wiring,
The magnetic beads and wires are pulled to the center tap on the chip side of the transformer.
12) There is no VDD between the PHY chip and the transformer, and the level between the PHY chip and the transformer
The surface area is defined as GND, which can cut off the noise path from the VDD plane.
13) Make a ground every 250mil along the edge of the single board PCB (no need to wrap PGND, see Figure 8)
These via holes can cut off the way for the board noise to radiate outward, and reduce the impact on the static ground of PGND.
14) The PGND and GND of the single board are connected to the structure through screw holes to ensure the unity of the system ground potential.
15) Ensure good decoupling (low resistance) between the power plane and the ground plane, and the power plane is best
The ground planes are adjacent.
16) The signal lines adjacent to the power plane should not exceed the projection area of the power plane.
17) To ensure the integrity of the return path of the signal line adjacent to the power plane,
Otherwise, it is necessary to change the shape of the plane, so that the signal line is in the plane layer, and the incomplete return path will cause serious EMC problems.
18) It is recommended to route all high-speed signal lines, I/O lines, and differential line pairs close to the ground plane first. If it is not possible, use the power plane as a reference plane.
19) The differential line should be far away from other signal lines, and place other signal lines to couple noise to the differential line.
20) In order to reduce the noise of the differential signal, the digital signal line or power supply should be far away from the analog signal line or power supply.
21) The decoupling and bypassing of the power supply are very important. They can provide a low impedance path for the signal and reduce the resonance between the power supply and the ground plane. Capacitors can play the role of decoupling and bypassing, but it is necessary to ensure that the area of the decoupling and bypassing capacitor loop composed of capacitors, traces, vias, and pads is as small as possible, and the inductance of the leads is as small as possible, as shown in the figure below shown
Figure 9 The loop area of the decoupling capacitor
Figure 10 Comparison of layout and wiring of transformer center tap common mode capacitors
7.2. PCB layout and wiring rules of network port circuit using integrated connector
Only the differences are described below.
1) The network port transformer is an isolation device, which is used to cut off the common mode. Because it has been integrated in the connector, the ground plane is no longer divided.
2) The shell of the integral connector should be connected to a continuous ground plane. Do not create a rack ground under the connector.
3) Drill ground vias every 250mil around the board to shield the noise of the board inside the board.
A very important point (referring to the design of the computer motherboard): For the metal shell of the grounding device exposed outside the chassis, contact discharge (such as 232 USB Ethernet interface, etc.), and the protection measures for their signal lines such as GDT pressure-sensitive TVS, etc. It should be connected to the metal casing, that is, the earth, and released to the earth (the metal casing of the grounding device is generally connected to the earth)