2.1 Processor
2.1.1 General Purpose Processor
At present, the mainstream general-purpose processors mostly adopt the chip design method of SoC (system on chip), integrating various functional modules, each function is designed by the hardware description language, and then realized by the circuit in the SoC. In the SoC, each module is not a mature ASIC ( application-
specific integrated circuit
) device, but uses a part of the chip's resources to implement a traditional function, and combines various components in a similar way to building blocks.
The design technology of the ARM core is licensed to hundreds of semiconductor manufacturers to make different SoC chips. ARM has very low power consumption and is widely used in today's most active wireless local area networks, 3G, mobile terminals, handheld devices, and wired network communication devices. Most smartphones and tablets on the market use ARM SoC as the main control chip. Many ARM main control chips have a very high level of integration. In addition to integrating multi-core ARM, they may also integrate a series of functions such as graphics processors, video codecs, floating-point coprocessors, GPS, WiFi, Bluetooth, baseband, and Camera. For example, Qualcomm's Snapdragon 810 integrates various modules as shown in Figure 2.1.
Figure 2.1 Example of ARM SoC: Snapdragon 810
Mainstream ARM mobile processing chip suppliers include Qualcomm, Samsung, Nvidia, Marvell, MTK, HiSilicon, Spreadtrum, etc. Texas Instruments (TI) and Broadcom (Broadcom) have faded out of the mobile phone chip business.
The architecture of the central processing unit is divided into two categories, one is the von Neumann structure, and the other is the Harvard structure. Intel's central processing unit, ARM's ARM7, and MIPS' MIPS processor use the von Neumann structure; ARM9, ARM10, ARM11, and Cortex A series use the Harvard structure.
The Von Neumann structure is a storage structure that combines program instruction memory and data memory. Program instruction storage addresses and data storage addresses point to different physical locations in the same memory, so program instructions and data have the same width. The Harvard structure stores program instructions and data separately, and instructions and data can have different data widths. In addition, the Harvard structure also adopts an independent program bus and data bus, which are used as dedicated communication paths between the CPU and each memory respectively, and have high execution efficiency. Figure 2.2 depicts the difference between the von Neumann structure and the Harvard structure.
Figure 2.2 Von Neumann structure and Harvard structure
Many chips use the improved Harvard structure as shown in Figure 2.3, which has independent address bus and data bus, and the two buses are shared by program memory and data memory in time-sharing. The improved Harvard structure is aimed at programs and data. In fact, there is no independent bus, but a common data bus is used to complete the data transmission between the program storage module or the data storage module and the CPU, and the common address bus is used to address programs and data.
From the point of view of the instruction set, the central processing unit can also be divided into two categories, RSIC (reduced instruction set computer) and CSIC (complex instruction set computer). CSIC emphasizes enhancing the ability of instructions and reducing the number of object codes, but the instructions are complex and the instruction cycle is long; while RSIC emphasizes minimizing the instruction set and single-cycle execution of instructions, but the object code will be larger. ARM, MIPS, PowerPC and other CPU cores all use the RISC instruction set. At present, the fusion of both RSIC and CSIC is very obvious.
Figure 2.3 Modified Harvard structure
2.1.2 Digital Signal Processor
Digital Signal Processors (DSPs) are designed for algorithms in areas such as communications, image, voice, and video processing. It contains independent hardware multipliers. The multiplication instructions of DSP are generally completed in a single cycle, and a large number of repetitive algorithms in algorithms such as convolution, digital filtering, FFT (fast Fourier transform), and correlation matrix operations are optimized.
DSP is divided into two categories, one is fixed-point DSP, and the other is floating-point DSP. Fixed-point DSP can only use fixed-point operations to simulate floating-point operations. The floating-point operations of floating-point DSPs are implemented in hardware and can be completed in a single cycle, so the processing speed of floating-point operations is higher than that of fixed-point DSPs.
Texas Instruments (TI) and American Analog Devices (ADI) are the two major manufacturers of DSP in the world.
General-purpose processors and digital signal processors also have a tendency to integrate each other to complement each other. For example, a digital signal controller (DSC) is MCU+DSP, and ADI's blackfin series belongs to DSC. At present, chip manufacturers have also introduced many dual-core and multi-core processors of ARM+DSP.
In addition to the general-purpose microcontrollers and digital signal processors mentioned above, there are also some special-purpose processors ASP designed for specific fields, all of which are designed for some specific applications, such as special-purpose processing for HDTV, ADSL, Cable Modem, etc. device.
A network processor is a programmable device that is used for various tasks in the telecommunications field, such as packet processing, protocol analysis, route lookup, voice/data aggregation, firewall, QoS, etc. The network processor device usually consists of several microcode processors and several hardware coprocessors. Multiple microcode processors are processed in parallel inside the network processor, and the processing flow is controlled by pre-programmed microcodes. For some complex standard operations (such as memory operations, routing table lookup algorithms, QoS congestion control algorithms, traffic scheduling algorithms, etc.), hardware coprocessors are used to further improve processing performance, thereby achieving business flexibility and high performance. organic combination.
For some applications, using an ASIC (application-specific integrated circuit) is often a low-cost and high-performance solution. ASICs are designed for specific applications and do not have or require flexible programming capabilities. Using ASIC to complete the same function is often cheaper and more efficient than directly using CPU resources or CPLD (Complex Programmable Logic Device)/FPGA (Field Programmable Gate Array). Processor classification as shown in Figure 2.4:
Figure 2.4 Processor Classification
In the hardware solution of the actual project, one of the solutions of general-purpose processor, digital signal processor, domain-specific processor, CPLD/FPGA or ASIC will be selected according to the needs of the application. In complex systems, these chips may be simultaneously Existence, cooperation, and each play their own strengths. For example, in a smart phone, the MCU can be used to process the graphical user interface and the user's key input and run a multitasking operating system, the DSP can be used to encode and decode audio and video, and the ASIC is used in the radio frequency.