Linux-driven design hardware foundation (4) SD and SDIO of interface and bus

2.3.7 SD and SDIO

    SD (Secure Digital) is a standard for Flash memory card, which is a common SD memory card, which is compatible with MMC (Multi-Media Card) in design. SDHC (SD High Capacity) is a large-capacity SD card with a maximum supported capacity of 32GB. SDXC (SD eXtended Capacity) released in 2009 supports a maximum capacity of 2TB.

    SDIO (Secure Digital Input and Output Card) defines peripheral interfaces other than memory cards on the basis of SD standard. There are two main categories of SDIO applications - removable and non-removable. Non-removable devices follow the same electrical standards, but do not require physical standards. Now there are many mobile phones or handheld devices that support SDIO functions to connect modules such as WiFi, Bluetooth, and GPS.

    Under normal circumstances, the SD controller integrated in the chip supports both MMC, SD card and SDIO card, but the protocols of SD and SDIO are still different, and the supported commands are also different.

The transmission modes of SD/SDIO are:
SPI mode
1-bit mode

4-bit mode

Table 2.1 SDIO interface pin definition


Table 2.1 shows the pin definitions of the SDIO interface. Among them, CLK is the clock pin, which transmits one command or data bit per clock cycle; CMD is the command pin, and the command is serially transmitted on the CMD line, which is bidirectional half-duplex (the command goes from the host to the slave card, while the command The response is sent from the card to the host); DAT[0]~DAT[3] are the data line pins; the 8th pin is regarded as an interrupt signal.

Figure 2.18 shows the typical timing for reading and writing a single SDIO module.


Figure 2.18 Typical timing of SDIO single module read and write

    eMMC (Embedded Multi Media Card) is the current mainstream solution for local storage of mobile devices, which aims to simplify the design of mobile phone storage. eMMC is a collection of NAND Flash, flash memory control chips and standard interface packages. It directly packages NAND and control chips together into a Multi-Chip Package (MCP) chip. eMMC supports DAT[0]~DAT[7] 8-bit data lines. After power-on or reset, it is in 1-bit mode by default, only DAT[0] is enabled, and it can be configured to 4-bit or 8-bit mode later.







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