Hardware foundation of Linux driver design

0, opening description

The content of this film is mainly from Mr. Song Baohua's "Linux Device Driver Development"

1. Processor

At present, mainstream general-purpose processors (GPP) mostly use SoC (system on chip) chip design methods to integrate various functional modules. The ARM core design technology is licensed to hundreds of semiconductor manufacturers to make different SoC chips. ARM's power consumption is very low, and it is widely used in today's most active wireless local area networks, 3G, mobile terminals, handheld devices, and wired network communication equipment. Many ARM master chips are highly integrated. In addition to integrating multi-core ARM, they may also integrate a series of functions such as graphics processors, video codecs, floating point coprocessors, GPS, WiFi, Bluetooth, baseband, and Camera.

The mainstream suppliers are as follows:

Qualcomm
Samsung (Samsung)
Nvidia
Marvell
MediaTek (MTK)
HiSilicon
Spreadtrum
Texas Instruments (TI)
Broadcom

The architecture of the central processing unit

Von Neumann (program instruction memory and data memory together)
Harvard structure (program and data are stored separately)

As shown in the figure below:
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instruction set

RISK
CICS

2. Memory

The memory classification is shown in the figure below:
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2.1 Flash read interface

NOR Flash Read and Write Interface (SRAM): Common Flash Interface (CFI) is a public, standard interface for reading data from NOR Flash devices.

NAND Flash interface:

I/O bus: Address, instruction and data are transmitted through this group of buses, generally 8 or 16 bits.
Chip Enable (CE#): If the CE signal is not detected, the NAND device remains in standby mode and does not respond to any control signals.
Write Enable (WE#): WE# is responsible for writing data, address or instructions into NAND.
Read Enable (RE#): RE# allows data output.
Command Latch Enable (CLE): When CLE is high, the command will be latched into the NAND command register on the rising edge of the WE# signal.
Address Latch Enable (ALE): When ALE is high, the address will be latched into the NAND address register on the rising edge of the WE# signal.
Ready/Busy (Ready/Busy, R/B#): If the NAND device is busy, the R/B# signal will go low. This signal is open-drain and requires a pull-up resistor.

2.2 Comparison of advantages and disadvantages of Flash

model	price	capacity	Erase times	speed
NOR	high	small	100,000	slow
NAND	low	Big	1000000	fast

2.3 RAM introduction

DRAM:
DRAM is stored in the form of electric charge, and data is stored in capacitors. Since the capacitor will lose charge due to leakage, DRAM devices need to be refreshed regularly
SRAM:
SRAM is static, it will maintain a value as long as power is supplied, SRAM has no refresh cycle
DPRAM: It
has two completely independent data buses, address buses and read-write control lines, which can be accessed at the same time by ports
CAM
content addressed memory. For data query
FIFO is
used for data buffering

3. Interface and bus

3.1 Serial port

RS-232
RS-422
RS-485 and
above are all formulated and released by EIA.

The RS-232C standard interface has 25 lines and 9 common lines:

RTS: Used to indicate that DTE requests DCE to send data. When the terminal wants to send data, the signal is valid.
CTS: Used to indicate that DCE is ready to receive data from DTE, which is a response signal to RTS.
RxD: DTE receives serial data sent from DCE through RxD.
TxD: DTE transfers serial data through TxD
DSR: Valid (ON state) indicates that DCE can be used.
DTR: Valid (ON state) indicates that DTE can be used.
DCD: When the local DCE device receives the carrier signal sent by the other party's DCE device, it makes the DCD valid, informs the DTE to be ready to receive, and the DCE demodulates the received carrier signal into a digital signal and sends it to the DTE via the RxD line.
Ringing-RI: When the modem receives the ringing call signal sent by the exchange, it makes the signal valid (ON state) to notify the terminal that it has been called.
SG: Ground signal

The simplest RS-232C serial port only needs to connect RxD, TxD, SG these 3 signals, and use XON/XOFF software flow control. Connect as shown in the figure below

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3.2 I2C

There are two buses:

SDA: Data bus
SDL: Clock bus

"Line and" logic

Requirements:
1) The output terminal of the device connected to the bus must be open-drain output or open-collector output.
2) When idle, the pull-up resistor must ensure that both wires are high level

The serial data line SDA interface circuit on the I2C device is bidirectional, the output circuit is used to send data to the bus, and the input circuit is used to receive data on the bus. Similarly, the serial clock line SCL is also bidirectional. As the host controlling the data transfer on the bus, it sends a clock signal through the SCL output circuit, and detects the level on the SCL on the bus to determine when to send the next clock pulse level; The slave device receiving the host command needs to send or receive the signal on the SDA according to the signal on the bus, and it can also send a low-level signal to the SCL line to extend the cycle of the bus clock signal. When SCL is stable at high level, the change of SDA from high to low will produce a start bit, and the change from low to high will produce a stop bit, as shown in Figure 2.10. Both the start bit and the stop bit are generated by the I2C master. When selecting a slave device, if the slave device uses a 7-bit address, the master device needs to send 1 byte of address information before initiating the transmission process, the first 7 bits are the device address, and the last 1 bit is the read and write flag. After that, the data transmitted each time is also 1 byte, starting from the MSB. After each byte is transmitted, the receiver should send an ACK bit before the 9th rising edge of SCL. The clock pulse on SCL is sent by the I2C master. After the 8th clock cycle, the master should release the SDA
start bit and stop bit diagram:
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I2C timing diagram:

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3.3 SPI

The SPI (Serial Peripheral Interface, serial peripheral interface) bus system is a synchronous serial peripheral interface, which allows the CPU to communicate with various peripheral devices in a serial manner to exchange information. Generally, the master SoC acts as the "master" of SPI, and the peripherals act as the "slave" of SPI.

SPI four lines:

Serial clock line SCLK
Host input/slave output data line MISO
Master output/slave input data line MOSI
Active low slave select line SS

Master and slave hardware connection diagram:

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In the transmission of the SPI bus, the SS signal is active at low level. When we want to communicate with a peripheral, we need to set the SS line on the peripheral to low. In addition, pay special attention to the highest clock frequency of the SPI bus supported by the SPI slave device (which determines the frequency of SCK) and the CPHA and CPOL modes of the peripherals.

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In order to exchange data with peripherals, the SPI module outputs serial synchronous clock polarity (CPOL) and phase (CPHA) according to the work requirements of the peripherals. If CPOL=0, the idle state of the serial synchronous clock is low; if CPOL=1, the idle state of the serial synchronous clock is high. If CPHA=0, the data is sampled on the first edge (rising or falling) of the serial synchronous clock; if CPHA=1, the data is sampled on the second edge (rising or falling) of the serial synchronous clock sampling.

3.4 USB

USB2.0：

480Mbit/s, half duplex
Four lines

USB3.0:

5.0Gbit/s, full duplex
The nine-wire

USB3.0 is compatible with USB2.0.
The physical topology of the USB host, device and HUB:

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Four transmission modes of USB endpoints:

control
Synchronize
Interrupt
batch

3.5 Ethernet

composition:

MAC: Ethernet Media Access Controller
PHY: Physical interface transceiver
Hardware circuit principle:

3.6 SD/SDIO

SD (Secure Digital) is a standard for Flash memory cards, which is a common SD memory card, which is designed to be compatible with MMC (Multi-Media Card). SDHC (SD High Capacity) is a large-capacity SD card with a maximum capacity of 32GB. The SDXC (SD eXtended Capacity) released in 2009 supports a maximum capacity of 2TB. SDIO (Secure Digital Input and Output Card, Secure Digital Input and Output Card) is based on the SD standard and defines peripheral interfaces other than memory cards. Nowadays, many mobile phones or handheld devices support SDIO function to connect WiFi, Bluetooth, GPS and other modules.
SD/SDIO transmission mode:

SPI
1-bit mode
4-bit mode

3.7 Schematic

slightly

3.8 Hardware timing