2.3.2 I2C
The I2C (Integrated Integrated Circuit) bus is a two-wire serial bus developed by Philips, which was created in the 1980s to connect microcontrollers and their peripherals. The I2C bus is simple and effective, occupies a small PCB (printed circuit board) space, has a small number of chip pins, and has a low design cost. The I2C bus supports Multi-Mastering mode, and any device capable of sending and receiving can become the master device. The master can control the transmission of data and the clock frequency, and there can only be one master at any time.
The two signals that make up the I2C bus are the data line SDA and the clock SCL. In order to avoid the confusion of the bus signal, it is required that the output end of each device connected to the bus must be an open-drain output or an open-collector output structure.
The open-drain output means that no voltage is output, and it is grounded when it is low, and it is not grounded when it is high. If an external pull-up resistor is connected, the voltage will be pulled up to the power supply voltage of the pull-up resistor when outputting a high level.
The principle of open-collector output is that when the triode is turned on, the collector outputs a low level; when the triode is turned off, the collector output is suspended, and the circuit needs an external load resistor and power supply during operation. As long as the resistance value of the resistor and the value of the power supply voltage are properly selected, it can be ensured that the high and low levels of the output meet the requirements, and the load current of the output triode is not too large.
Pull-up resistors keep both the SDA and SCL lines high . According to the "wire-and" logic of the open-drain output or open-collector output signal, any device on the I2C bus outputs a low level, and the signal line on the corresponding bus goes low.
The serial data line SDA interface circuit on the I2C device is bidirectional, the output circuit is used to send data to the bus, and the input circuit is used to receive the data on the bus. Similarly, the serial clock line SCL is also bidirectional. As the host that controls the data transmission of the bus, it sends a clock signal through the SCL output circuit, and detects the level on the SCL on the bus to determine when to send the next clock pulse level; as a The slave device that receives the master command needs to send or receive the signal on SDA according to the signal of SCL on the bus, and it can also send a low level signal to the SCL line to prolong the period of the bus clock signal.
When SCL is stable high, a high-to-low transition of SDA will generate a start bit, and a low-to-high transition will generate a stop bit, as shown in Figure 2.10.
Figure 2.10 Start bit and stop bit of I2C bus
Both start and stop bits are generated by the I2C master. When selecting a slave device, if the slave device adopts a 7-bit address, the master device needs to send 1 byte of address information before initiating the transmission process. The first 7 bits are the device address, and the last 1 bit is the read and write flag. After that, the data transmitted each time is also 1 byte, starting from the MSB (most significant bit). After each byte is transmitted, the receiver should send an ACK (response) bit before the ninth rising edge of SCL. The clock pulse on SCL is sent by the I2C master. After the 8th clock cycle, the master should release SDA. The timing of the I2C bus is shown in Figure 2.11.
Figure 2.11 Timing of I2C bus