A TDM overview
Audio TDM (Time-Division Multiplexing) protocol is a communication protocol for combining multiple audio signals into one signal. It slices multiple audio signals by time and combines them into a continuous digital stream, so as to transmit multiple audio signals at the same time. It is currently widely used in the field of intelligent cockpit audio.
Figure 1 Schematic diagram of TDM data transmission
Figure 1 shows a schematic diagram of TDM data transmission. Each audio signal is assigned a fixed slot (time slot), and these slots are arranged in sequence to form a frame. The length of each slot is equal and fixed, and can accommodate the data of an audio signal. Data for multiple audio signals is interleaved by filling each slot in turn in a pre-agreed order.
At the sending end, the audio TDM protocol places the sample values of multiple audio signals in corresponding slots respectively.
At the receiving end, the protocol takes out the slot data in the same order and restores them to the original audio signal. In this way, multiple audio signals can be transmitted on the same channel at the same time, which realizes efficient utilization of channel resources.
Note : The slot mentioned above has no direct correspondence with the audio channel. It is related to the actual chip platform and Codec definition. It cannot be simply said that slot1 understands the first channel of bit audio data. For example, assuming that the length of slot1 is 32 bits, slot1 can transmit two channels of 16-bit audio data. This flexibility allows the length of the time slot and the format of the audio signal carried by each time slot to be determined according to specific requirements and agreements in different TDM implementations.
Two TDM signal definitions
Audio TDM determines the clock rate and timing of data transfers by using BLCK as the bit clock signal. The Frame Sync signal is used to identify the beginning and end of the audio frame to ensure correct combination and analysis of audio data. The Data IN and Data OUT signal pins are used to input and output audio data to realize the combination and transmission of multiple audio signals.
BLCK (Bit Clock) : BLCK pin is a clock signal pin in audio TDM. During each BLCK clock cycle, only one data bit can be transferred. The frequency of the BLCK signal determines the rate of data transmission, and each data bit is transmitted within one clock cycle. The sending end fills data bits sequentially in each time slot, and transmits the data bits according to the edge of the BLCK signal in each BLCK clock cycle. The receiving end samples and analyzes the data bits according to the clock edge of the BLCK signal to restore the audio signal.
Frame Sync (frame synchronization) : The Frame Sync pin is used to identify the beginning and end of a data frame. In audio TDM, multiple slots are combined into a complete audio frame. A state change of the Frame Sync signal indicates the start of a new audio frame. The receiving end identifies and parses the data of each slot according to the Frame Sync signal, and combines it into the original audio signal.
SD IN pin : The SD IN pin is a pin for inputting audio data.
SD OUT pin : The SD OUT pin is a pin for outputting audio data.
| I2S |
TDM |
|
| bit clock |
BLCK |
BLCK |
| sync signal |
WS (left and right channels) |
Frame Sync |
| data input |
SD IN |
SD IN |
| data output |
SD OUT |
SD Out |
In I2S, the left and right channels are distinguished through the WS pin, and each sample is transmitted alternately by the left and right channels. In TDM, the Frame Sync signal is used to identify the start and end of the audio frame, and an audio frame can contain multiple slots.
Three master-slave mode
There are two basic modes of TDM transmission: master mode (Master Mode) and slave mode (Slave Mode).
3.1 Master Mode
In master mode, a device is configured as a master device or master clock source. The master device is responsible for generating clock signals and controlling the timing of the entire TDM transmission. It determines the rate, channel order and frame structure of the transfer. The other devices transmit in slave mode and are synchronized to the master's clock signal. Master mode is suitable for controlling the main equipment of the whole TDM system.
3.2 Slave Mode
In slave mode, the device is configured as a slave device or a slave clock source. The slave device receives the clock signal sent by the master device, and transmits data according to the clock signal. A device in slave mode needs to be synchronized with the timing of the master device to ensure accurate data transmission. Slave mode is for secondary devices that cooperate with the primary device.
Four TDM transmission timing
At present, there is no uniform standard to define the mode and timing of TDM transmission. Different manufacturers may have different descriptions of TDM transmission, but they will provide flexible configuration methods. When performing TDM transmission configuration, it is necessary to carefully compare the specifications of the system chip (SoC) and external CODEC to understand the specific configuration requirements. This article will take the specifications of the AKM CODEC chip as an example to roughly introduce the TDM transmission mode.
The clock rate of the TDM protocol is equal to the sampling rate multiplied by the TDM frame length. For a system with 8 slots, 32bit audio data per slot, and a sampling rate of 48kHz, the BCLK clock rate of TDM is: 8 × 32 × 48kHz = 12.288 MHz. In the Datasheet of the device, you can find terms such as TDM128/TDM256/TDM384/TDM512. These numbers indicate the number of data bits contained in a single TDM data frame (that is, the frame length). For example, 8 slot, 32bit audio data is also called TDM256 (=8*32).
4.1 Mode 0 I2S Compatiable Format
图2 TDM mode I2S Compatiable（TDM256）
As shown in Figure 2, the characteristics of this transmission mode:
- When the falling edge of the frame synchronization signal indicates the start of a frame of data, the low level maintains the N/2 slot width, and then changes to a high level until the next frame of data starts to go low again.
- When each frame of data starts to be transmitted, the valid data is delayed by one bit clock, that is, the rising edge of the second BICK after the start of the frame synchronization signal is the first valid data bit.
4.2 Mode 1 MSB Justified Format
图3 TDM mode MSB Justified Format（TDM256）
As shown in Figure 3, the characteristics of this transmission mode:
- The rising and falling edges of the frame synchronization signal represent the start of a frame of data, and the high level maintains the N/2 slot width, and then changes to a low level until the next frame of data starts to become high again.
- When each frame of data starts to be transmitted, there is no delay in the effective data bits, and the transmission is aligned from the left
4.3 Mode 2 LSB Justified Format
图4 TDM mode LSB Justified Format（TDM256）
As shown in Figure 4, the characteristics of this transmission mode:
- The rising and falling edges of the frame synchronization signal represent the start of a frame of data, and the high level maintains the N/2 slot width and then changes to a low level until the next frame of data starts to become high again.
- When each frame of data starts to be transmitted, there is no delay in the valid data bits, and the transmission is aligned from the right
4.4 Mode 3 PCM Short Frame Format
Figure 5 TDM mode PCM Short Frame (TDM256)
As shown in Figure 5, the characteristics of this transmission mode:
- The rising and falling edges of the frame synchronization signal represent the beginning of a frame of data, and the high level only maintains a bit clock width until the next frame of data starts to become high again, which is also the width of a bit clock.
- In addition to valid slots, a frame of data may have other filling data (Don't Care).
- When each frame of data starts to be transmitted, the valid data is delayed by one bit clock, that is, the rising edge of the second BICK after the start of the frame synchronization signal is the first valid data bit.
4.5 Mode 4 PCM Long Frame Format
Figure 6 TDM mode PCM Long Frame (TDM256)
As shown in Figure 6, the characteristics of this transmission mode:
- The rising and falling edges of the frame synchronization signal represent the beginning of a frame of data, and the high level only maintains a bit clock width until the next frame of data starts to become high again, which is also the width of a bit clock.
- In addition to valid slots, a frame of data may have other filling data.
- Valid data bits are not delayed at the start of each frame of data transmission
4.6 Mode 5 Irregular I2S Format
图7 TDM mode Irregular I2S Format（TDM256）
As shown in Figure 7, the characteristics of this transmission mode:
- When the falling edge of the frame synchronization signal indicates the start of a frame of data, the low level maintains the N/2 slot (valid data) width, and then becomes high until the next frame of data starts to go low again.
- When each frame of data starts to be transmitted, the valid data is delayed by one bit clock, that is, the rising edge of the second BICK after the start of the frame synchronization signal is the first valid data bit.
- In addition to valid slots, a frame of data also has other filling data.