1. Introduction to VCS
VCS is a compiled Verilog simulator, which fully supports OVI standard Verilog HDL language, PLI and SDF. VCS has the highest analog performance in the industry, and its excellent memory management capability is sufficient to support ASIC design at tens of millions of gates, and its analog accuracy fully meets the requirements of deep submicron ASIC Sign-Off.
The processing of files by VCS is mainly divided into the following parts:
Raw .v file input.
into a .c file.
compiled into an executable binary.
Finally, generate simv to view the simulation results.
VCS has a three-step method and a two-step method. The three-step method is used to simulate a mixed language, such as a mixture of Verilog and VHDL, while the two-step method is used to simulate a single language. Generally, only the Verilog language is simulated, so only the two-step method is introduced here. .