Verilog implementation of divide-by-three

module fre_div3 (q,clk,reset);
    output q;
    input reset;
    input clk;
    
    reg q1,q2;               
    reg [1:0] count_a,count_b;

    assign q=q1^q2; // two different ORs are the output q we want to get

    always @ (posedge clk or posedge reset) //q1；
    if (reset)
    begin
      q1<=1'b0;
      count_a<=2'b00;
    end
      else if(count_a==0)
        begin
         q1<=~q1;
         count_a<=count_a+1'b1;
        end
        else if(count_a==2)
        begin
           count_a<=0;
        end
        else 

            begin

               count_a<=count_a+1'b1;

                count_a<=2'b00;
            end
       
       
    always @ (negedge clk or posedge reset)    
    if (reset)
    begin
      q2<=1'b0;
      count2<=2'b00;
end
      else if(count2==0)
        begin
         q2<=~q2;
         count2<=count2+1'b1;
        end
        else if(count2==1'b1)
        begin
            q2=~q2;
            count2<=count2+1'b1;
        end
            else 
            begin
                count2<=2'b00;
            end
      

      endmodule