Comparison analysis and Verilog implementation of various adders (3)

       The previous blog introduced the Kogge-Stone adder and the brent-kung adder, and this article will implement it with Verilog code. Please see the principle part:

Comparison analysis of various adders and Verilog implementation (2)_Albert_yeager's blog

1. Verilog implementation of Kogge-Stone adder

module koggle_stone (
input  [3:0] a_i,b_i,
input  c_i,
output wire [3:0] c_o
);
wire [3:0] q,p;
wire [4:0] carry;

assign p = a_i & b_i;
assign q = a_i | b_i;
assign carry[0] = c_i;
assign carry[1] = p[0] + q[0] & carry[0]; 
assign carry[2] = p[1] + q[1] & p[0] + q[1] & q[0] & carry[0]; 
assign carry[3] = p[2] + q[2] & p[1] + q[2] & q[1] & carry[1]; 
assign carry[4] = p[3] + q[3] & p[2] + q[3] & q[2] & carry[2]; 

assign c_o[3:0] = a_i ^ b_i ^ carry[3:0];
assign c_o[4] = carry[4];
endmodule

Kogge-Stone adder circuit synthesized by Vivado

 2. Verilog implementation of brent-kung adder

module brent_kung (
input [2:0] a_i,b_i,
input c_i,
output wire [3:0] c_o
);
wire [2:0] q,p,carry;
wire [1:0] level_0_p,level_0_q;
wire [1:0] level_1_p,level_1_q;

assign p = a_i & b_i;
assign q = a_i | b_i;

CELL level_0_tree0 (
	.p_1(p[0]),	
	.q_1(q[0]),	
	.p_0(1'b0),	
	.q_0(c_i),
	.P(level_0_p[0]),	
	.Q(level_0_q[0])
);

CELL level_0_tree1 (
	.p_1(p[2]),	
	.q_1(q[2]),	
	.p_0(p[1]),	
	.q_0(q[1]),
	.P(level_0_p[1]),	
	.Q(level_0_q[1])
);

CELL level_1_tree0 (
	.p_1(p[1]),			
	.q_1(q[1]),
	.p_0(level_0_p[0]),	
	.q_0(level_0_q[0]),
	.P(level_1_p[0]),	
	.Q(level_1_q[0])
);
CELL level_1_tree1 (
	.p_1(level_0_p[1]),	
	.q_1(level_0_q[1]),
	.p_0(level_0_p[0]),	
	.q_0(level_0_q[0]),
	.P(level_1_p[1]),	
	.Q(level_1_q[1])
);

assign carry[0] = level_0_p[0] | level_0_q[0];
assign carry[1] = level_1_p[0] | level_1_q[0];
assign carry[2] = level_1_p[1] | level_1_q[1];
assign c_o[3] = carry[2];
assign c_o[2:0] = a_i ^ b_i ^ {carry[1:0],c_i};

endmodule

The brent-kung adder circuit synthesized by Vivado

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