Function 1: counting function
Four registers are involved
1. 16-bit timer-----counter register(TIMx_CNT)
2. 16-bit prescaler register----prescaler register(TIMx_PSC)
3. 16-bit auto-reload loading register----auto-reloader register(TIMx_ARR)
4. Repeat register----repetition counter register(TIMx_RCR)
Basic introduction to registers:
1. Automatic reload register ( TIMx_ARR): If the number in this register is A, after the counter counts to A, an event (update event) will be generated. [Requires UDIS bit to be 0]
When the timer is working, the register that actually takes effect is not ARR, but another register, called the shadow register. There are two working modes depending on the configuration. One is that the ARR and the shadow register are continuously connected, so that the data in the shadow register is always the same as the data in ARR, and they can be regarded as the same register; the other is that the data in the shadow register is always the same as the data in the ARR. The data in the ARR is written to the shadow register only when the update event (UEV) occurs. These two working modes can be switched by changing the ARPE bit (in the TIMx_CR1 register). When ARPE is 0, it works in the first case, as shown in Figure 201; when ARPE is 1, it works in the second case, such as Figure 202 .
As shown in Figure 201 above, the ARPE bit is 0, and the value 36 written to TIMx_ARR takes effect immediately.
As shown in Figure 202 above, the ARPE bit is 1, and the value written in TIMx_ARR will not take effect until UEV is generated.
2. Prescaler register (TIMx_PSC): The counter needs a clock to drive, and the frequency of the clock is controlled by this register.
This register can be written with new data at any time, but the new data will not take effect immediately after writing the new data, and it will take effect after the next update event (UEV) . At the same time, this register will generate the divided clock only after the CEN bit (in the TIMx_CR1 register) is set.
For example, in the figure below, when the CEN bit is set, the clock CK_CNT is generated, and the drive counter starts counting. When the counter has not reached the threshold, the value of the prescaler register (TIMx_PSC) is changed, and the clock frequency does not change. Until the counter reaches the threshold and an update event (UEV) is generated, the clock frequency becomes half of the original.
3. Repeat register (TIMx_RCR) : If the number in TIMx_ARR is A and the number in the repeat register is N, then the counter needs to count to A for N+1 consecutive times to generate an event (UEV).
The following describes several basic counting modes
1. Upcounting mode
If the repeat register is not set (meaning that the TIMx_RCR holds the reset value of 0 ), the counter will count up from 0 until the set threshold ( the number in the shadow register ), and then generate an update event (UEV) with an up Overflow event (counter overflow event), and then repeat the above process from 0.
If the value in the repeat register is set to N (that is , the number in TIMx_RCR is N ), the counter counts from 0 to the threshold, and repeats this process (N+1) times, after the (N+1)th count reaches the threshold , which generates an update event (UEV).
Note: We can generate update events (UEV) in software, just set the UG bit (in register TIMx_EGR).
在前面的寄存器基本功能介绍中，有这样一句话“1、自动重装载寄存器(TIMx_ARR)：假如该寄存器中的数为A，则计数器计数到A后，会产生一个事件(update event)。【需要UDIS位为0】。”说明我们可以通过将UDIS位（在寄存器TIMx_CR1）置位来屏蔽更新事件(UEV)的产生。在官方文档[1]中解释了屏蔽UEV的目的，这样做是为了避免当我们正在向自动重装载寄存器(TIMx_ARR)中写数的时候，UEV产生，导致自动重装载寄存器(TIMx_ARR)里的数被更新到影子寄存器。因此我们向TIMx_ARR写数的时候最好屏蔽掉UEV，写完后再解除屏蔽。
[1] RM0410 Reference manual STM32F76xxx and STM32F77xxx advanced Arm®-based 32-bit MCUs.