STM32 HAL library development series - TIM timer function
clock source
The timer must have a clock source to achieve counting. The basic timer clock can only come from the internal clock, and the advanced control timer and general-purpose timer can also choose an external clock source or directly from other timer waiting modes. We can set the clock frequency of all timers through the TIMPRE bit of the RCC dedicated clock configuration register (RCC_DCKCFGR). We generally set this bit to the default value of 0, that is, TIMxCLK is twice the bus clock, making the optional in Table 31‑1 The maximum timer clock is 84MHz, that is, the internal clock (CK_INT) frequency of the basic timer is 84MHz.
The basic timer can only use the internal clock. When the CEN bit of TIM6 and TIM7 control register 1 (TIMx_CR1) is set to 1, the basic timer is started, and the clock source of the prescaler is CK_INT. For the clock sources of advanced control timers and general-purpose timers, you can find the external clock of the controller, other timers, etc.
controller
The timer controller controls and realizes the timer function, and the basic function of controlling timer reset, enabling, and counting is its basic function. The basic timer is also specially used for DAC conversion triggering.
counter
The counting process of the basic timer mainly involves the content of three registers, namely the counter register (TIMx_CNT), the prescaler register (TIMx_PSC), and the automatic reload register (TIMx_ARR). These three registers are all 16-bit significant figures, namely The value can be set from 0 to 65535.
First, let's look at the prescaler PSC in Figure 31‑1, which has an input clock CK_PSC and an output clock CK_CNT. The input clock CK_PSC comes from the controller part, and the basic timer only has an internal clock source, so CK_PSC is actually equal to CK_INT, which is 84MHz. In different applications, different timing frequencies are often required. It is very convenient to obtain different CK_CNT by setting the value of the prescaler PSC. The actual calculation is: fCK_CNT is equal to fCK_PSC/(PSC[15:0]+1).
Figure 31‑2 shows the changing process of the counter clock when the value of the prescaler PSC is changed from 1 to 4. It turns out that the frequency is divided by 1, and the frequency of CK_PSC and CK_CNT is the same. When writing a new value to the TIMx_PSC register, the CK_CNT output frequency will not be updated immediately, but when the update event occurs, the value of the TIMx_PSC register will be updated to the shadow register to make it really effective. After updating to divide by 4, CK_CNT will generate a pulse after 4 consecutive pulses of CK_PSC appear.
Timer Period Calculation
After the above analysis, we know that the timing event generation time is mainly determined by the two register values of TIMx_PSC and TIMx_ARR, which is the period of the timer. For example, we need a timer with a period of 1s, how to set the values of these two registers. Assume that we first set the TIMx_ARR register value to 9999, that is, when TIMx_CNT counts from 0 and is exactly equal to 9999, an event is generated, and the total count is 10,000 times. If the clock source period is 100us at this time, the timing period of exactly 1s can be obtained.
The next problem is to set the TIMx_PSC register value so that the CK_CNT output is a 100us period (10000Hz) clock. The input clock CK_PSC of the prescaler is 84MHz, so setting the value of the prescaler to (8400-1) is sufficient.
References and citations: STM32F4xx Reference Manual, STM32F4xx Specification, Wildfire Open Source Project, Library Help Documentation