The configuration speed of the four channels of stm103c8t6 tim1 is different (resolved)

    Using this chip, TIM1 is used to output four PWM signals. When changing the duty cycle, it is found that the speed of CH1 is normal, and CH2, CH3, and CH4 will take effect after a small delay.

At present, the cause of the problem has not been found. If a big cow knows, you can reply to the younger brother below. Below is the code.

void PWM4_Init(u32 arr,u32 psc)
{  
	
			
			
	
         GPIO_InitTypeDef GPIO_InitStructure;
        TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
        TIM_OCInitTypeDef  TIM_OCInitStructure;
       
        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_TIM1|RCC_APB2Periph_AFIO , ENABLE); //Enable GPIO peripheral clock enable
                                                                                     
                                                                             

   //Set this pin to multiplex output function, output the PWM pulse waveform of TIM1 CH1
			GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9|GPIO_Pin_10|GPIO_Pin_11 ; //TIM_CH1
        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; //Multiplex push-pull output
        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
        GPIO_Init(GPIOA, &GPIO_InitStructure);


        TIM_TimeBaseStructure.TIM_Period = arr; //Set the value 80K of the active auto-reload register period loaded on the next update event
        TIM_TimeBaseStructure.TIM_Prescaler =psc; //Set the prescaler value used as the divisor of the TIMx clock frequency without dividing
        TIM_TimeBaseStructure.TIM_ClockDivision =0; //Set the clock division: TDTS = Tck_tim
        TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; //TIM count up mode
        TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); //Initialize the time base unit of TIMx according to the parameters specified in TIM_TimeBaseInitStruct
//TIM1 channel one
        TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; //Select timer mode: TIM pulse width modulation mode 2
        TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; //Compare output enable
        TIM_OCInitStructure.TIM_Pulse = 100; /*duty length 0 – period(max)*/
        TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; //Output polarity: TIM output compare polarity is high
        TIM_OC1Init(TIM1, &TIM_OCInitStructure); //Initialize the peripheral TIMx according to the parameters specified in TIM_OCInitStruct
//TIM1 channel two
  TIM_OCInitStructure.TIM_OutputState =TIM_OutputState_Enable;
  TIM_OCInitStructure.TIM_Pulse = 100; /*duty length 0 – period(max)*/
  TIM_OC2Init(TIM1, &TIM_OCInitStructure);
  TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
//TIM1 channel three
  TIM_OCInitStructure.TIM_OutputState =TIM_OutputState_Enable;
  TIM_OCInitStructure.TIM_Pulse = 100; /*duty length 0 – period(max)*/
  TIM_OC3Init(TIM1, &TIM_OCInitStructure);
  TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
//TIM1 channel four
  TIM_OCInitStructure.TIM_OutputState =TIM_OutputState_Enable;
  TIM_OCInitStructure.TIM_Pulse = 100; /*duty length 0 – period(max)*/
  TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Enable);

  TIM_CtrlPWMOutputs(TIM1,ENABLE); //MOE main output enable        
  TIM_ARRPreloadConfig(TIM1, ENABLE); //Enable TIMx preload register on ARR
        TIM_Cmd(TIM1, ENABLE); //Enable TIM1
}

		while(1)
	{
	//	LED0=!LED0;
	
	// TIM_Cmd(TIM1, DISABLE); //Enable TIM1	
	TIM1-> CCR1 = 50;
	TIM1->CCR2=50;
	TIM1->CCR3=50;
	TIM1->CCR4=50;
	// TIM_Cmd(TIM1, ENABLE); //Enable TIM1	
		//delay_ms(1000);
		delay_ms(1000);
		delay_ms(1000);
	//TIM_Cmd(TIM1, DISABLE); //Enable TIM1
	TIM1-> CCR1 = 250;
	TIM1->CCR2=250;
	TIM1->CCR3=250;
	TIM1->CCR4=250;
	//TIM_Cmd(TIM1, ENABLE); //Enable TIM1	

			//delay_ms(1000);
			delay_ms(1000);
			delay_ms(1000);
	}
	

The main function continuously updates the duty cycle value. CH2, CH3, CH4 take effect slower than CH1, as seen by the oscilloscope.

Resolution time: 18-5-14-------------------------------------------- -------------------------------------------------- ---------------------------------------
The reason for this is that the registers are not fully configured due to library functions.


It is necessary to change OC1PE, OC2PE, OC3PE, OC4PE in CCMR1 and CCMR2 to 1 or 0, and the four channels will be synchronized.
0 means the register value can be written at any time
TIM1->CCMR1&=0xF7F7; //Close event update value
TIM1->CCMR2&=0xF7F7;
1 means that the register value is updated only when there is an update event
        TIM1->CCMR1|=0x808; //Enable event update value
TIM1->CCMR2|=0x808;