TIM advanced timer theoretical knowledge (Part 2)
Hello, everyone, due to the training of the national flag escort and the rain last night, it was very late to return to the dormitory, so I had a pigeon for a day. Please forgive me.
Okay, let’s get back to the subject. In the issue the day before yesterday, I explained to you the two parts of the clock source and controller. Today, I will talk about the other two parts: time base and input capture.
The time base unit is actually relatively simple. Its flow chart is as follows:
Its components are divided into four parts:
1. 16bit prescaler PSC
2. 16bit counter CNT
3. 8bit repeat counter RCR
4. 16bit Automatic reload register ARR
Is this flowchart familiar to everyone? It is similar to the basic timer block diagram we saw before, the only difference is that it has an extra repeat counter. When the repeat counter is counting up, it will not generate an update interrupt when it counts to ARR, at this time REP+1; while counting down, when ARR becomes 0, REP-1.
Well, there is no other introduction in the time base part, and the next thing is the focus.
Input capture
Input capture can capture the rising edge, falling edge or both sides of the input signal. Commonly used are measuring the pulse width of the input signal and measuring the frequency and duty cycle of the PWM input signal.
The general principle of input capture is: when the signal transition edge is captured, the value of the counter CNT is latched into the capture register CCR, and the value in the CCR register captured two times before and after is subtracted to calculate it. Pulse width or frequency, if the captured pulse width or frequency, if the duration of the captured pulse width exceeds the period of the timer you capture, overflow will occur.
Its functional block diagram is as follows:
We need to learn the following five points when learning input capture:
1.
When the input channel uses the signal to be measured , it enters from the timer's external pin TIMx_CH1/2/3/4, usually called TI1/2/3/4 , In the subsequent capture explanation, the signal to be measured is called TIx as the standard.
2. Input filtering and edge detection
When the input signal has high frequency interference, we need to filter the input signal, that is, re-sampling. According to the sampling law, the sampling frequency must be greater than 2 times the input signal. For example, if the input signal is 1M and there is high-frequency signal interference, it is necessary to filter at this time. At this time, the sampling frequency can be set to 2M, so that it can be higher than 2M on the basis of ensuring that the effective signal is sampled. The high frequency signal is filtered out.
The configuration of the filter is controlled by the bits CKD[1:0] of the CRI register and the bits ICxF[3:0] of CCMR1/2. From the description of the ICxF bits, the sampling frequency fSAMPLE can be provided by the clock divided by fCK_INT and fDTS , Where fCK_INT is the internal clock, fDTS is the frequency obtained after fCK_INT is divided, the frequency division factor is determined by CKD[1:0], which can be no frequency division, 2 frequency division, or 4 frequency division.
The edge detector is used to set which edge is valid when the signal is captured. It can be rising edge, falling edge, double edge. The details are determined by the bits CCxP and CCxNP of the CCER register.
3. Capture channel The
capture channel is IC1/2/3/4, and each capture channel has a corresponding capture register CCR1/2/3/4. When a capture occurs, the value of the counter CNT will be latched To the capture register.
! ! !
What should be noted here is the difference between the input channel and the capture channel.
Input channels are used to input signals, and capture channels are used to capture input signals. One input signal channel can be input to two capture channels at the same time. For example, after the signal of the input channel TI1 passes through the filter edge detector, TI1FP1 and TI1FP2 can enter the capture channels IC1 and IC2. When you only need to measure the pulse width of the input signal, use one capture channel. The mapping relationship between the two is specifically configured with the bits CCxS[1:0] of the register CCMRx.
4. Prescaler
(1) The output signal of ICx will pass through a prescaler to determine how many events occur once. Capture
(2) The bit ICxPSC configuration of the specific register CCMRx, if you want to capture each edge of the signal, do not divide the frequency.
5.
The signal ICxPS of the capture register passing through the prescaler is the final captured signal. When the first capture occurs, the value of the counter CNT will be locked in the capture register CCR, and a CCxI interrupt will also be generated, and the corresponding interrupt bit CCxIF (in the SR register) will be set, and CCxIF can be cleared by software or by reading the value in CCR. If the second capture occurs (that is, the counter value captured by the CCR register is repeatedly captured and the CCxIF flag is set to 1), the capture overflow flag CCxOF (in the SR register) will be set, and CCxOF can only be cleared by software .
These are the two parts. Tomorrow is the third part. Let's talk about an output comparison. It has the same effect as today's input capture. I hope everyone will study hard.